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chenhuacaichenhuacai
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LoongArch: Adjust common macro definitions for 32BIT/64BIT
Most common macros are defined in asm.h, asmmacro.h and stackframe.h. Adjust these macros for both 32BIT and 64BIT. Add SETUP_TWINS (Setup Trampoline Windows) and SETUP_MODES (Setup CRMD/ PRMD/EUEN) which will be used later. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
1 parent 81f5d15 commit 708ed32

3 files changed

Lines changed: 174 additions & 55 deletions

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‎arch/loongarch/include/asm/asm.h‎

Lines changed: 57 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -72,11 +72,11 @@
7272
#define INT_SUB sub.w
7373
#define INT_L ld.w
7474
#define INT_S st.w
75-
#define INT_SLL slli.w
75+
#define INT_SLLI slli.w
7676
#define INT_SLLV sll.w
77-
#define INT_SRL srli.w
77+
#define INT_SRLI srli.w
7878
#define INT_SRLV srl.w
79-
#define INT_SRA srai.w
79+
#define INT_SRAI srai.w
8080
#define INT_SRAV sra.w
8181
#endif
8282

@@ -86,11 +86,11 @@
8686
#define INT_SUB sub.d
8787
#define INT_L ld.d
8888
#define INT_S st.d
89-
#define INT_SLL slli.d
89+
#define INT_SLLI slli.d
9090
#define INT_SLLV sll.d
91-
#define INT_SRL srli.d
91+
#define INT_SRLI srli.d
9292
#define INT_SRLV srl.d
93-
#define INT_SRA srai.d
93+
#define INT_SRAI srai.d
9494
#define INT_SRAV sra.d
9595
#endif
9696

@@ -100,15 +100,23 @@
100100
#if (__SIZEOF_LONG__ == 4)
101101
#define LONG_ADD add.w
102102
#define LONG_ADDI addi.w
103+
#define LONG_ALSL alsl.w
104+
#define LONG_BSTRINS bstrins.w
105+
#define LONG_BSTRPICK bstrpick.w
103106
#define LONG_SUB sub.w
104107
#define LONG_L ld.w
108+
#define LONG_LI li.w
109+
#define LONG_LPTR ld.w
105110
#define LONG_S st.w
106-
#define LONG_SLL slli.w
111+
#define LONG_SPTR st.w
112+
#define LONG_SLLI slli.w
107113
#define LONG_SLLV sll.w
108-
#define LONG_SRL srli.w
114+
#define LONG_SRLI srli.w
109115
#define LONG_SRLV srl.w
110-
#define LONG_SRA srai.w
116+
#define LONG_SRAI srai.w
111117
#define LONG_SRAV sra.w
118+
#define LONG_ROTR rotr.w
119+
#define LONG_ROTRI rotri.w
112120

113121
#ifdef __ASSEMBLER__
114122
#define LONG .word
@@ -121,15 +129,23 @@
121129
#if (__SIZEOF_LONG__ == 8)
122130
#define LONG_ADD add.d
123131
#define LONG_ADDI addi.d
132+
#define LONG_ALSL alsl.d
133+
#define LONG_BSTRINS bstrins.d
134+
#define LONG_BSTRPICK bstrpick.d
124135
#define LONG_SUB sub.d
125136
#define LONG_L ld.d
137+
#define LONG_LI li.d
138+
#define LONG_LPTR ldptr.d
126139
#define LONG_S st.d
127-
#define LONG_SLL slli.d
140+
#define LONG_SPTR stptr.d
141+
#define LONG_SLLI slli.d
128142
#define LONG_SLLV sll.d
129-
#define LONG_SRL srli.d
143+
#define LONG_SRLI srli.d
130144
#define LONG_SRLV srl.d
131-
#define LONG_SRA srai.d
145+
#define LONG_SRAI srai.d
132146
#define LONG_SRAV sra.d
147+
#define LONG_ROTR rotr.d
148+
#define LONG_ROTRI rotri.d
133149

134150
#ifdef __ASSEMBLER__
135151
#define LONG .dword
@@ -145,16 +161,23 @@
145161
#if (__SIZEOF_POINTER__ == 4)
146162
#define PTR_ADD add.w
147163
#define PTR_ADDI addi.w
164+
#define PTR_ALSL alsl.w
165+
#define PTR_BSTRINS bstrins.w
166+
#define PTR_BSTRPICK bstrpick.w
148167
#define PTR_SUB sub.w
149168
#define PTR_L ld.w
150-
#define PTR_S st.w
151169
#define PTR_LI li.w
152-
#define PTR_SLL slli.w
170+
#define PTR_LPTR ld.w
171+
#define PTR_S st.w
172+
#define PTR_SPTR st.w
173+
#define PTR_SLLI slli.w
153174
#define PTR_SLLV sll.w
154-
#define PTR_SRL srli.w
175+
#define PTR_SRLI srli.w
155176
#define PTR_SRLV srl.w
156-
#define PTR_SRA srai.w
177+
#define PTR_SRAI srai.w
157178
#define PTR_SRAV sra.w
179+
#define PTR_ROTR rotr.w
180+
#define PTR_ROTRI rotri.w
158181

159182
#define PTR_SCALESHIFT 2
160183

@@ -168,16 +191,23 @@
168191
#if (__SIZEOF_POINTER__ == 8)
169192
#define PTR_ADD add.d
170193
#define PTR_ADDI addi.d
194+
#define PTR_ALSL alsl.d
195+
#define PTR_BSTRINS bstrins.d
196+
#define PTR_BSTRPICK bstrpick.d
171197
#define PTR_SUB sub.d
172198
#define PTR_L ld.d
173-
#define PTR_S st.d
174199
#define PTR_LI li.d
175-
#define PTR_SLL slli.d
200+
#define PTR_LPTR ldptr.d
201+
#define PTR_S st.d
202+
#define PTR_SPTR stptr.d
203+
#define PTR_SLLI slli.d
176204
#define PTR_SLLV sll.d
177-
#define PTR_SRL srli.d
205+
#define PTR_SRLI srli.d
178206
#define PTR_SRLV srl.d
179-
#define PTR_SRA srai.d
207+
#define PTR_SRAI srai.d
180208
#define PTR_SRAV sra.d
209+
#define PTR_ROTR rotr.d
210+
#define PTR_ROTRI rotri.d
181211

182212
#define PTR_SCALESHIFT 3
183213

@@ -190,10 +220,17 @@
190220

191221
/* Annotate a function as being unsuitable for kprobes. */
192222
#ifdef CONFIG_KPROBES
223+
#ifdef CONFIG_32BIT
224+
#define _ASM_NOKPROBE(name) \
225+
.pushsection "_kprobe_blacklist", "aw"; \
226+
.long name; \
227+
.popsection
228+
#else
193229
#define _ASM_NOKPROBE(name) \
194230
.pushsection "_kprobe_blacklist", "aw"; \
195231
.quad name; \
196232
.popsection
233+
#endif
197234
#else
198235
#define _ASM_NOKPROBE(name)
199236
#endif

‎arch/loongarch/include/asm/asmmacro.h‎

Lines changed: 90 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -5,43 +5,55 @@
55
#ifndef _ASM_ASMMACRO_H
66
#define _ASM_ASMMACRO_H
77

8+
#include <linux/sizes.h>
89
#include <asm/asm-offsets.h>
910
#include <asm/regdef.h>
1011
#include <asm/fpregdef.h>
1112
#include <asm/loongarch.h>
1213

14+
#ifdef CONFIG_64BIT
15+
#define TASK_STRUCT_OFFSET 0
16+
#else
17+
#define TASK_STRUCT_OFFSET 2000
18+
#endif
19+
1320
.macro cpu_save_nonscratch thread
14-
stptr.d s0, \thread, THREAD_REG23
15-
stptr.d s1, \thread, THREAD_REG24
16-
stptr.d s2, \thread, THREAD_REG25
17-
stptr.d s3, \thread, THREAD_REG26
18-
stptr.d s4, \thread, THREAD_REG27
19-
stptr.d s5, \thread, THREAD_REG28
20-
stptr.d s6, \thread, THREAD_REG29
21-
stptr.d s7, \thread, THREAD_REG30
22-
stptr.d s8, \thread, THREAD_REG31
23-
stptr.d sp, \thread, THREAD_REG03
24-
stptr.d fp, \thread, THREAD_REG22
21+
LONG_SPTR s0, \thread, (THREAD_REG23 - TASK_STRUCT_OFFSET)
22+
LONG_SPTR s1, \thread, (THREAD_REG24 - TASK_STRUCT_OFFSET)
23+
LONG_SPTR s2, \thread, (THREAD_REG25 - TASK_STRUCT_OFFSET)
24+
LONG_SPTR s3, \thread, (THREAD_REG26 - TASK_STRUCT_OFFSET)
25+
LONG_SPTR s4, \thread, (THREAD_REG27 - TASK_STRUCT_OFFSET)
26+
LONG_SPTR s5, \thread, (THREAD_REG28 - TASK_STRUCT_OFFSET)
27+
LONG_SPTR s6, \thread, (THREAD_REG29 - TASK_STRUCT_OFFSET)
28+
LONG_SPTR s7, \thread, (THREAD_REG30 - TASK_STRUCT_OFFSET)
29+
LONG_SPTR s8, \thread, (THREAD_REG31 - TASK_STRUCT_OFFSET)
30+
LONG_SPTR ra, \thread, (THREAD_REG01 - TASK_STRUCT_OFFSET)
31+
LONG_SPTR sp, \thread, (THREAD_REG03 - TASK_STRUCT_OFFSET)
32+
LONG_SPTR fp, \thread, (THREAD_REG22 - TASK_STRUCT_OFFSET)
2533
.endm
2634

2735
.macro cpu_restore_nonscratch thread
28-
ldptr.d s0, \thread, THREAD_REG23
29-
ldptr.d s1, \thread, THREAD_REG24
30-
ldptr.d s2, \thread, THREAD_REG25
31-
ldptr.d s3, \thread, THREAD_REG26
32-
ldptr.d s4, \thread, THREAD_REG27
33-
ldptr.d s5, \thread, THREAD_REG28
34-
ldptr.d s6, \thread, THREAD_REG29
35-
ldptr.d s7, \thread, THREAD_REG30
36-
ldptr.d s8, \thread, THREAD_REG31
37-
ldptr.d ra, \thread, THREAD_REG01
38-
ldptr.d sp, \thread, THREAD_REG03
39-
ldptr.d fp, \thread, THREAD_REG22
36+
LONG_LPTR s0, \thread, (THREAD_REG23 - TASK_STRUCT_OFFSET)
37+
LONG_LPTR s1, \thread, (THREAD_REG24 - TASK_STRUCT_OFFSET)
38+
LONG_LPTR s2, \thread, (THREAD_REG25 - TASK_STRUCT_OFFSET)
39+
LONG_LPTR s3, \thread, (THREAD_REG26 - TASK_STRUCT_OFFSET)
40+
LONG_LPTR s4, \thread, (THREAD_REG27 - TASK_STRUCT_OFFSET)
41+
LONG_LPTR s5, \thread, (THREAD_REG28 - TASK_STRUCT_OFFSET)
42+
LONG_LPTR s6, \thread, (THREAD_REG29 - TASK_STRUCT_OFFSET)
43+
LONG_LPTR s7, \thread, (THREAD_REG30 - TASK_STRUCT_OFFSET)
44+
LONG_LPTR s8, \thread, (THREAD_REG31 - TASK_STRUCT_OFFSET)
45+
LONG_LPTR ra, \thread, (THREAD_REG01 - TASK_STRUCT_OFFSET)
46+
LONG_LPTR sp, \thread, (THREAD_REG03 - TASK_STRUCT_OFFSET)
47+
LONG_LPTR fp, \thread, (THREAD_REG22 - TASK_STRUCT_OFFSET)
4048
.endm
4149

4250
.macro fpu_save_csr thread tmp
4351
movfcsr2gr \tmp, fcsr0
52+
#ifdef CONFIG_32BIT
53+
st.w \tmp, \thread, THREAD_FCSR
54+
#else
4455
stptr.w \tmp, \thread, THREAD_FCSR
56+
#endif
4557
#ifdef CONFIG_CPU_HAS_LBT
4658
/* TM bit is always 0 if LBT not supported */
4759
andi \tmp, \tmp, FPU_CSR_TM
@@ -56,7 +68,11 @@
5668
.endm
5769

5870
.macro fpu_restore_csr thread tmp0 tmp1
71+
#ifdef CONFIG_32BIT
72+
ld.w \tmp0, \thread, THREAD_FCSR
73+
#else
5974
ldptr.w \tmp0, \thread, THREAD_FCSR
75+
#endif
6076
movgr2fcsr fcsr0, \tmp0
6177
#ifdef CONFIG_CPU_HAS_LBT
6278
/* TM bit is always 0 if LBT not supported */
@@ -88,9 +104,52 @@
88104
#endif
89105
.endm
90106

107+
#ifdef CONFIG_32BIT
91108
.macro fpu_save_cc thread tmp0 tmp1
92109
movcf2gr \tmp0, $fcc0
93-
move \tmp1, \tmp0
110+
move \tmp1, \tmp0
111+
movcf2gr \tmp0, $fcc1
112+
bstrins.w \tmp1, \tmp0, 15, 8
113+
movcf2gr \tmp0, $fcc2
114+
bstrins.w \tmp1, \tmp0, 23, 16
115+
movcf2gr \tmp0, $fcc3
116+
bstrins.w \tmp1, \tmp0, 31, 24
117+
st.w \tmp1, \thread, THREAD_FCC
118+
movcf2gr \tmp0, $fcc4
119+
move \tmp1, \tmp0
120+
movcf2gr \tmp0, $fcc5
121+
bstrins.w \tmp1, \tmp0, 15, 8
122+
movcf2gr \tmp0, $fcc6
123+
bstrins.w \tmp1, \tmp0, 23, 16
124+
movcf2gr \tmp0, $fcc7
125+
bstrins.w \tmp1, \tmp0, 31, 24
126+
st.w \tmp1, \thread, (THREAD_FCC + 4)
127+
.endm
128+
129+
.macro fpu_restore_cc thread tmp0 tmp1
130+
ld.w \tmp0, \thread, THREAD_FCC
131+
bstrpick.w \tmp1, \tmp0, 7, 0
132+
movgr2cf $fcc0, \tmp1
133+
bstrpick.w \tmp1, \tmp0, 15, 8
134+
movgr2cf $fcc1, \tmp1
135+
bstrpick.w \tmp1, \tmp0, 23, 16
136+
movgr2cf $fcc2, \tmp1
137+
bstrpick.w \tmp1, \tmp0, 31, 24
138+
movgr2cf $fcc3, \tmp1
139+
ld.w \tmp0, \thread, (THREAD_FCC + 4)
140+
bstrpick.w \tmp1, \tmp0, 7, 0
141+
movgr2cf $fcc4, \tmp1
142+
bstrpick.w \tmp1, \tmp0, 15, 8
143+
movgr2cf $fcc5, \tmp1
144+
bstrpick.w \tmp1, \tmp0, 23, 16
145+
movgr2cf $fcc6, \tmp1
146+
bstrpick.w \tmp1, \tmp0, 31, 24
147+
movgr2cf $fcc7, \tmp1
148+
.endm
149+
#else
150+
.macro fpu_save_cc thread tmp0 tmp1
151+
movcf2gr \tmp0, $fcc0
152+
move \tmp1, \tmp0
94153
movcf2gr \tmp0, $fcc1
95154
bstrins.d \tmp1, \tmp0, 15, 8
96155
movcf2gr \tmp0, $fcc2
@@ -109,7 +168,7 @@
109168
.endm
110169

111170
.macro fpu_restore_cc thread tmp0 tmp1
112-
ldptr.d \tmp0, \thread, THREAD_FCC
171+
ldptr.d \tmp0, \thread, THREAD_FCC
113172
bstrpick.d \tmp1, \tmp0, 7, 0
114173
movgr2cf $fcc0, \tmp1
115174
bstrpick.d \tmp1, \tmp0, 15, 8
@@ -127,6 +186,7 @@
127186
bstrpick.d \tmp1, \tmp0, 63, 56
128187
movgr2cf $fcc7, \tmp1
129188
.endm
189+
#endif
130190

131191
.macro fpu_save_double thread tmp
132192
li.w \tmp, THREAD_FPR0
@@ -606,12 +666,14 @@
606666
766:
607667
lu12i.w \reg, 0
608668
ori \reg, \reg, 0
669+
#ifdef CONFIG_64BIT
609670
lu32i.d \reg, 0
610671
lu52i.d \reg, \reg, 0
672+
#endif
611673
.pushsection ".la_abs", "aw", %progbits
612-
.p2align 3
613-
.dword 766b
614-
.dword \sym
674+
.p2align PTRLOG
675+
PTR 766b
676+
PTR \sym
615677
.popsection
616678
#endif
617679
.endm

‎arch/loongarch/include/asm/stackframe.h‎

Lines changed: 27 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -38,22 +38,42 @@
3838
cfi_restore \reg \offset \docfi
3939
.endm
4040

41+
.macro SETUP_TWINS temp
42+
pcaddi t0, 0
43+
PTR_LI t1, ~TO_PHYS_MASK
44+
and t0, t0, t1
45+
ori t0, t0, (1 << 4 | 1)
46+
csrwr t0, LOONGARCH_CSR_DMWIN0
47+
PTR_LI t0, CSR_DMW1_INIT
48+
csrwr t0, LOONGARCH_CSR_DMWIN1
49+
.endm
50+
51+
.macro SETUP_MODES temp
52+
/* Enable PG */
53+
li.w \temp, 0xb0 # PLV=0, IE=0, PG=1
54+
csrwr \temp, LOONGARCH_CSR_CRMD
55+
li.w \temp, 0x04 # PLV=0, PIE=1, PWE=0
56+
csrwr \temp, LOONGARCH_CSR_PRMD
57+
li.w \temp, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0
58+
csrwr \temp, LOONGARCH_CSR_EUEN
59+
.endm
60+
4161
.macro SETUP_DMWINS temp
42-
li.d \temp, CSR_DMW0_INIT # WUC, PLV0, 0x8000 xxxx xxxx xxxx
62+
PTR_LI \temp, CSR_DMW0_INIT # SUC, PLV0, LA32: 0x8xxx xxxx, LA64: 0x8000 xxxx xxxx xxxx
4363
csrwr \temp, LOONGARCH_CSR_DMWIN0
44-
li.d \temp, CSR_DMW1_INIT # CAC, PLV0, 0x9000 xxxx xxxx xxxx
64+
PTR_LI \temp, CSR_DMW1_INIT # CAC, PLV0, LA32: 0xaxxx xxxx, LA64: 0x9000 xxxx xxxx xxxx
4565
csrwr \temp, LOONGARCH_CSR_DMWIN1
46-
li.d \temp, CSR_DMW2_INIT # WUC, PLV0, 0xa000 xxxx xxxx xxxx
66+
PTR_LI \temp, CSR_DMW2_INIT # WUC, PLV0, LA32: unavailable, LA64: 0xa000 xxxx xxxx xxxx
4767
csrwr \temp, LOONGARCH_CSR_DMWIN2
48-
li.d \temp, CSR_DMW3_INIT # 0x0, unused
68+
PTR_LI \temp, CSR_DMW3_INIT # 0x0, unused
4969
csrwr \temp, LOONGARCH_CSR_DMWIN3
5070
.endm
5171

5272
/* Jump to the runtime virtual address. */
5373
.macro JUMP_VIRT_ADDR temp1 temp2
54-
li.d \temp1, CACHE_BASE
74+
PTR_LI \temp1, CACHE_BASE
5575
pcaddi \temp2, 0
56-
bstrins.d \temp1, \temp2, (DMW_PABITS - 1), 0
76+
PTR_BSTRINS \temp1, \temp2, (DMW_PABITS - 1), 0
5777
jirl zero, \temp1, 0xc
5878
.endm
5979

@@ -171,7 +191,7 @@
171191
andi t0, t0, 0x3 /* extract pplv bit */
172192
beqz t0, 9f
173193

174-
li.d tp, ~_THREAD_MASK
194+
LONG_LI tp, ~_THREAD_MASK
175195
and tp, tp, sp
176196
cfi_st u0, PT_R21, \docfi
177197
csrrd u0, PERCPU_BASE_KS

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