Skip to content

Commit 7095d21

Browse files
bjorn-helgaasbjorn-helgaas
committed
Merge branch 'pci/dt-bindings'
- Add "apb", "sys", "pmc", "msg", "err" for Endpoint descriptions as well as for Root Complexes (Niklas Cassel) - Add "tx_inta", "tx_intb", "tx_intc", "tx_intd" for interrupt signals triggered in response to PCIe Assert_INTx messages (Niklas Cassel) - Refactor rockchip-dw-pcie binding to move generic properties to a new rockchip-dw-pcie-common binding that can be shared by both RC and EP mode (Niklas Cassel) - Fix rockchip-dw-pcie description of INTx signals (Niklas Cassel) - Add rockchip-dw-pcie description of Endpoint controller (Niklas Cassel) - Avoid xilinx-versal-cpm overlapping of bridge registers and 32-bit BAR addresses (Thippeswamy Havalige) - Add qcom Operating Performance Points (OPP) table (Krishna chaitanya chundru) - Add a picture of mediatek,mt7621-pcie topology (Sergio Paracuellos) - Add a generic "ats-supported" property so the OS can discover whether a Root Complex supports ATS (Jean-Philippe Brucker) - Make the qcom,pcie-x1e80100 MHI register region mandatory (Abel Vesa) * pci/dt-bindings: dt-bindings: PCI: qcom: x1e80100: Make the MHI reg region mandatory dt-bindings: PCI: generic: Add ats-supported property dt-bindings: PCI: mediatek,mt7621-pcie: Add PCIe host topology ASCII graph dt-bindings: PCI: qcom: Add OPP table dt-bindings: PCI: xilinx-cpm: Fix overlapping of bridge register and 32-bit BAR addresses dt-bindings: PCI: rockchip: Add DesignWare based PCIe Endpoint controller dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy IRQ dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy IRQs dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name
2 parents 65d8f68 + 30e7c6c commit 7095d21

9 files changed

Lines changed: 276 additions & 95 deletions

‎Documentation/devicetree/bindings/pci/host-generic-pci.yaml‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,12 @@ properties:
110110
iommu-map-mask: true
111111
msi-parent: true
112112

113+
ats-supported:
114+
description:
115+
Indicates that a PCIe host controller supports ATS, and can handle Memory
116+
Requests with Address Type (AT).
117+
type: boolean
118+
113119
required:
114120
- compatible
115121
- reg

‎Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,35 @@ description: |+
1313
MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
1414
with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
1515
16+
MT7621 PCIe HOST Topology
17+
18+
.-------.
19+
| |
20+
| CPU |
21+
| |
22+
'-------'
23+
|
24+
|
25+
|
26+
v
27+
.------------------.
28+
.-----------| HOST/PCI Bridge |------------.
29+
| '------------------' | Type1
30+
BUS0 | | | Access
31+
v v v On Bus0
32+
.-------------. .-------------. .-------------.
33+
| VIRTUAL P2P | | VIRTUAL P2P | | VIRTUAL P2P |
34+
| BUS0 | | BUS0 | | BUS0 |
35+
| DEV0 | | DEV1 | | DEV2 |
36+
'-------------' '-------------' '-------------'
37+
Type0 | Type0 | Type0 |
38+
Access BUS1 | Access BUS2| Access BUS3|
39+
On Bus1 v On Bus2 v On Bus3 v
40+
.----------. .----------. .----------.
41+
| Device 0 | | Device 0 | | Device 0 |
42+
| Func 0 | | Func 0 | | Func 0 |
43+
'----------' '----------' '----------'
44+
1645
allOf:
1746
- $ref: /schemas/pci/pci-host-bridge.yaml#
1847

‎Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,10 @@ properties:
6969
- const: msi6
7070
- const: msi7
7171

72+
operating-points-v2: true
73+
opp-table:
74+
type: object
75+
7276
resets:
7377
maxItems: 1
7478

‎Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,11 +19,10 @@ properties:
1919
const: qcom,pcie-x1e80100
2020

2121
reg:
22-
minItems: 5
22+
minItems: 6
2323
maxItems: 6
2424

2525
reg-names:
26-
minItems: 5
2726
items:
2827
- const: parf # Qualcomm specific registers
2928
- const: dbi # DesignWare PCIe registers

‎Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml‎

Lines changed: 126 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,126 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: DesignWare based PCIe RC/EP controller on Rockchip SoCs
8+
9+
maintainers:
10+
- Shawn Lin <shawn.lin@rock-chips.com>
11+
- Simon Xue <xxm@rock-chips.com>
12+
- Heiko Stuebner <heiko@sntech.de>
13+
14+
description: |+
15+
Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip
16+
SoCs.
17+
18+
properties:
19+
clocks:
20+
minItems: 5
21+
items:
22+
- description: AHB clock for PCIe master
23+
- description: AHB clock for PCIe slave
24+
- description: AHB clock for PCIe dbi
25+
- description: APB clock for PCIe
26+
- description: Auxiliary clock for PCIe
27+
- description: PIPE clock
28+
- description: Reference clock for PCIe
29+
30+
clock-names:
31+
minItems: 5
32+
items:
33+
- const: aclk_mst
34+
- const: aclk_slv
35+
- const: aclk_dbi
36+
- const: pclk
37+
- const: aux
38+
- const: pipe
39+
- const: ref
40+
41+
interrupts:
42+
minItems: 5
43+
items:
44+
- description:
45+
Combined system interrupt, which is used to signal the following
46+
interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
47+
hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
48+
edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
49+
- description:
50+
Combined PM interrupt, which is used to signal the following
51+
interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
52+
linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
53+
linkst_out_l0s, pm_dstate_update
54+
- description:
55+
Combined message interrupt, which is used to signal the following
56+
interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
57+
pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
58+
- description:
59+
Combined legacy interrupt, which is used to signal the following
60+
interrupts - inta, intb, intc, intd, tx_inta, tx_intb, tx_intc,
61+
tx_intd
62+
- description:
63+
Combined error interrupt, which is used to signal the following
64+
interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
65+
tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
66+
nf_err_rx, f_err_rx, radm_qoverflow
67+
- description:
68+
eDMA write channel 0 interrupt
69+
- description:
70+
eDMA write channel 1 interrupt
71+
- description:
72+
eDMA read channel 0 interrupt
73+
- description:
74+
eDMA read channel 1 interrupt
75+
76+
interrupt-names:
77+
minItems: 5
78+
items:
79+
- const: sys
80+
- const: pmc
81+
- const: msg
82+
- const: legacy
83+
- const: err
84+
- const: dma0
85+
- const: dma1
86+
- const: dma2
87+
- const: dma3
88+
89+
num-lanes: true
90+
91+
phys:
92+
maxItems: 1
93+
94+
phy-names:
95+
const: pcie-phy
96+
97+
power-domains:
98+
maxItems: 1
99+
100+
resets:
101+
minItems: 1
102+
maxItems: 2
103+
104+
reset-names:
105+
oneOf:
106+
- const: pipe
107+
- items:
108+
- const: pwr
109+
- const: pipe
110+
111+
required:
112+
- compatible
113+
- reg
114+
- reg-names
115+
- clocks
116+
- clock-names
117+
- num-lanes
118+
- phys
119+
- phy-names
120+
- power-domains
121+
- resets
122+
- reset-names
123+
124+
additionalProperties: true
125+
126+
...

‎Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml‎

Lines changed: 95 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,95 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: DesignWare based PCIe Endpoint controller on Rockchip SoCs
8+
9+
maintainers:
10+
- Niklas Cassel <cassel@kernel.org>
11+
12+
description: |+
13+
RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare
14+
PCIe IP and thus inherits all the common properties defined in
15+
snps,dw-pcie-ep.yaml.
16+
17+
allOf:
18+
- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
19+
- $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
20+
21+
properties:
22+
compatible:
23+
enum:
24+
- rockchip,rk3568-pcie-ep
25+
- rockchip,rk3588-pcie-ep
26+
27+
reg:
28+
items:
29+
- description: Data Bus Interface (DBI) registers
30+
- description: Data Bus Interface (DBI) shadow registers
31+
- description: Rockchip designed configuration registers
32+
- description: Memory region used to map remote RC address space
33+
- description: Internal Address Translation Unit (iATU) registers
34+
35+
reg-names:
36+
items:
37+
- const: dbi
38+
- const: dbi2
39+
- const: apb
40+
- const: addr_space
41+
- const: atu
42+
43+
required:
44+
- interrupts
45+
- interrupt-names
46+
47+
unevaluatedProperties: false
48+
49+
examples:
50+
- |
51+
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
52+
#include <dt-bindings/interrupt-controller/arm-gic.h>
53+
#include <dt-bindings/interrupt-controller/irq.h>
54+
#include <dt-bindings/power/rk3588-power.h>
55+
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
56+
57+
soc {
58+
#address-cells = <2>;
59+
#size-cells = <2>;
60+
61+
pcie3x4_ep: pcie-ep@fe150000 {
62+
compatible = "rockchip,rk3588-pcie-ep";
63+
reg = <0xa 0x40000000 0x0 0x00100000>,
64+
<0xa 0x40100000 0x0 0x00100000>,
65+
<0x0 0xfe150000 0x0 0x00010000>,
66+
<0x9 0x00000000 0x0 0x40000000>,
67+
<0xa 0x40300000 0x0 0x00100000>;
68+
reg-names = "dbi", "dbi2", "apb", "addr_space", "atu";
69+
clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
70+
<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
71+
<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
72+
clock-names = "aclk_mst", "aclk_slv",
73+
"aclk_dbi", "pclk",
74+
"aux", "pipe";
75+
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
76+
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
77+
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
78+
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
79+
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>,
80+
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>,
81+
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>,
82+
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>,
83+
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
84+
interrupt-names = "sys", "pmc", "msg", "legacy", "err",
85+
"dma0", "dma1", "dma2", "dma3";
86+
max-link-speed = <3>;
87+
num-lanes = <4>;
88+
phys = <&pcie30phy>;
89+
phy-names = "pcie-phy";
90+
power-domains = <&power RK3588_PD_PCIE>;
91+
resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
92+
reset-names = "pwr", "pipe";
93+
};
94+
};
95+
...

0 commit comments

Comments
 (0)