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quic-kdybcioRob Clark
quic-kdybcio
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Rob Clark
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soc: qcom: ubwc: Add #defines for UBWC swizzle bits
Make the values a bit more meaningful. This commit is intentionally cross-subsystem to ease review, as the patchset is intended to be merged together, with a maintainer consensus. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/660981/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
1 parent caf5ad1 commit 709dd2f

3 files changed

Lines changed: 30 additions & 17 deletions

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‎drivers/gpu/drm/msm/adreno/a6xx_gpu.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -680,7 +680,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
680680
BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);
681681
u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;
682682
bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0;
683-
u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1));
683+
u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL2);
684684
bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg);
685685
bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
686686
bool min_acc_len_64b = false;

‎drivers/soc/qcom/ubwc_config.c‎

Lines changed: 25 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ static const struct qcom_ubwc_cfg_data qcm2290_data = {
3232
static const struct qcom_ubwc_cfg_data sa8775p_data = {
3333
.ubwc_enc_version = UBWC_4_0,
3434
.ubwc_dec_version = UBWC_4_0,
35-
.ubwc_swizzle = 4,
35+
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL3,
3636
.ubwc_bank_spread = true,
3737
.highest_bank_bit = 13,
3838
.macrotile_mode = true,
@@ -41,7 +41,8 @@ static const struct qcom_ubwc_cfg_data sa8775p_data = {
4141
static const struct qcom_ubwc_cfg_data sar2130p_data = {
4242
.ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */
4343
.ubwc_dec_version = UBWC_4_3,
44-
.ubwc_swizzle = 6,
44+
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
45+
UBWC_SWIZZLE_ENABLE_LVL3,
4546
.ubwc_bank_spread = true,
4647
.highest_bank_bit = 13,
4748
.macrotile_mode = true,
@@ -50,15 +51,17 @@ static const struct qcom_ubwc_cfg_data sar2130p_data = {
5051
static const struct qcom_ubwc_cfg_data sc7180_data = {
5152
.ubwc_enc_version = UBWC_2_0,
5253
.ubwc_dec_version = UBWC_2_0,
53-
.ubwc_swizzle = 6,
54+
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
55+
UBWC_SWIZZLE_ENABLE_LVL3,
5456
.ubwc_bank_spread = true,
5557
.highest_bank_bit = 14,
5658
};
5759

5860
static const struct qcom_ubwc_cfg_data sc7280_data = {
5961
.ubwc_enc_version = UBWC_3_0,
6062
.ubwc_dec_version = UBWC_4_0,
61-
.ubwc_swizzle = 6,
63+
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
64+
UBWC_SWIZZLE_ENABLE_LVL3,
6265
.ubwc_bank_spread = true,
6366
.highest_bank_bit = 14,
6467
.macrotile_mode = true,
@@ -74,7 +77,8 @@ static const struct qcom_ubwc_cfg_data sc8180x_data = {
7477
static const struct qcom_ubwc_cfg_data sc8280xp_data = {
7578
.ubwc_enc_version = UBWC_4_0,
7679
.ubwc_dec_version = UBWC_4_0,
77-
.ubwc_swizzle = 6,
80+
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
81+
UBWC_SWIZZLE_ENABLE_LVL3,
7882
.ubwc_bank_spread = true,
7983
.highest_bank_bit = 16,
8084
.macrotile_mode = true,
@@ -95,15 +99,19 @@ static const struct qcom_ubwc_cfg_data sdm845_data = {
9599
static const struct qcom_ubwc_cfg_data sm6115_data = {
96100
.ubwc_enc_version = UBWC_1_0,
97101
.ubwc_dec_version = UBWC_2_0,
98-
.ubwc_swizzle = 7,
102+
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
103+
UBWC_SWIZZLE_ENABLE_LVL2 |
104+
UBWC_SWIZZLE_ENABLE_LVL3,
99105
.ubwc_bank_spread = true,
100106
.highest_bank_bit = 14,
101107
};
102108

103109
static const struct qcom_ubwc_cfg_data sm6125_data = {
104110
.ubwc_enc_version = UBWC_1_0,
105111
.ubwc_dec_version = UBWC_3_0,
106-
.ubwc_swizzle = 7,
112+
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
113+
UBWC_SWIZZLE_ENABLE_LVL2 |
114+
UBWC_SWIZZLE_ENABLE_LVL3,
107115
.highest_bank_bit = 14,
108116
};
109117

@@ -116,7 +124,8 @@ static const struct qcom_ubwc_cfg_data sm6150_data = {
116124
static const struct qcom_ubwc_cfg_data sm6350_data = {
117125
.ubwc_enc_version = UBWC_2_0,
118126
.ubwc_dec_version = UBWC_2_0,
119-
.ubwc_swizzle = 6,
127+
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
128+
UBWC_SWIZZLE_ENABLE_LVL3,
120129
.ubwc_bank_spread = true,
121130
.highest_bank_bit = 14,
122131
};
@@ -136,7 +145,8 @@ static const struct qcom_ubwc_cfg_data sm8150_data = {
136145
static const struct qcom_ubwc_cfg_data sm8250_data = {
137146
.ubwc_enc_version = UBWC_4_0,
138147
.ubwc_dec_version = UBWC_4_0,
139-
.ubwc_swizzle = 6,
148+
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
149+
UBWC_SWIZZLE_ENABLE_LVL3,
140150
.ubwc_bank_spread = true,
141151
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
142152
.highest_bank_bit = 16,
@@ -146,7 +156,8 @@ static const struct qcom_ubwc_cfg_data sm8250_data = {
146156
static const struct qcom_ubwc_cfg_data sm8350_data = {
147157
.ubwc_enc_version = UBWC_4_0,
148158
.ubwc_dec_version = UBWC_4_0,
149-
.ubwc_swizzle = 6,
159+
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
160+
UBWC_SWIZZLE_ENABLE_LVL3,
150161
.ubwc_bank_spread = true,
151162
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
152163
.highest_bank_bit = 16,
@@ -156,7 +167,8 @@ static const struct qcom_ubwc_cfg_data sm8350_data = {
156167
static const struct qcom_ubwc_cfg_data sm8550_data = {
157168
.ubwc_enc_version = UBWC_4_0,
158169
.ubwc_dec_version = UBWC_4_3,
159-
.ubwc_swizzle = 6,
170+
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
171+
UBWC_SWIZZLE_ENABLE_LVL3,
160172
.ubwc_bank_spread = true,
161173
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
162174
.highest_bank_bit = 16,
@@ -176,7 +188,8 @@ static const struct qcom_ubwc_cfg_data sm8750_data = {
176188
static const struct qcom_ubwc_cfg_data x1e80100_data = {
177189
.ubwc_enc_version = UBWC_4_0,
178190
.ubwc_dec_version = UBWC_4_3,
179-
.ubwc_swizzle = 6,
191+
.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
192+
UBWC_SWIZZLE_ENABLE_LVL3,
180193
.ubwc_bank_spread = true,
181194
/* TODO: highest_bank_bit = 15 for LP_DDR4 */
182195
.highest_bank_bit = 16,

‎include/linux/soc/qcom/ubwc.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -21,11 +21,11 @@ struct qcom_ubwc_cfg_data {
2121
* UBWC 1.0 always enables all three levels.
2222
* UBWC 2.0 removes level 1 bank swizzling, leaving levels 2 & 3.
2323
* UBWC 4.0 adds the optional ability to disable levels 2 & 3.
24-
*
25-
* This is a bitmask where BIT(0) enables level 1, BIT(1)
26-
* controls level 2, and BIT(2) enables level 3.
2724
*/
2825
u32 ubwc_swizzle;
26+
#define UBWC_SWIZZLE_ENABLE_LVL1 BIT(0)
27+
#define UBWC_SWIZZLE_ENABLE_LVL2 BIT(1)
28+
#define UBWC_SWIZZLE_ENABLE_LVL3 BIT(2)
2929

3030
/**
3131
* @highest_bank_bit: Highest Bank Bit
@@ -66,7 +66,7 @@ static inline bool qcom_ubwc_get_ubwc_mode(const struct qcom_ubwc_cfg_data *cfg)
6666
{
6767
bool ret = cfg->ubwc_enc_version == UBWC_1_0;
6868

69-
if (ret && !(cfg->ubwc_swizzle & BIT(0)))
69+
if (ret && !(cfg->ubwc_swizzle & UBWC_SWIZZLE_ENABLE_LVL1))
7070
pr_err("UBWC config discrepancy - level 1 swizzling disabled on UBWC 1.0\n");
7171

7272
return ret;

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