@@ -445,25 +445,11 @@ static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset,
445445{
446446 struct brcmf_chip_priv * ci ;
447447 int count ;
448- struct brcmf_core * d11core2 = NULL ;
449- struct brcmf_core_priv * d11priv2 = NULL ;
450448
451449 ci = core -> chip ;
452450
453- /* special handle two D11 cores reset */
454- if (core -> pub .id == BCMA_CORE_80211 ) {
455- d11core2 = brcmf_chip_get_d11core (& ci -> pub , 1 );
456- if (d11core2 ) {
457- brcmf_dbg (INFO , "found two d11 cores, reset both\n" );
458- d11priv2 = container_of (d11core2 ,
459- struct brcmf_core_priv , pub );
460- }
461- }
462-
463451 /* must disable first to work for arbitrary current core state */
464452 brcmf_chip_ai_coredisable (core , prereset , reset );
465- if (d11priv2 )
466- brcmf_chip_ai_coredisable (d11priv2 , prereset , reset );
467453
468454 count = 0 ;
469455 while (ci -> ops -> read32 (ci -> ctx , core -> wrapbase + BCMA_RESET_CTL ) &
@@ -475,30 +461,9 @@ static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset,
475461 usleep_range (40 , 60 );
476462 }
477463
478- if (d11priv2 ) {
479- count = 0 ;
480- while (ci -> ops -> read32 (ci -> ctx ,
481- d11priv2 -> wrapbase + BCMA_RESET_CTL ) &
482- BCMA_RESET_CTL_RESET ) {
483- ci -> ops -> write32 (ci -> ctx ,
484- d11priv2 -> wrapbase + BCMA_RESET_CTL ,
485- 0 );
486- count ++ ;
487- if (count > 50 )
488- break ;
489- usleep_range (40 , 60 );
490- }
491- }
492-
493464 ci -> ops -> write32 (ci -> ctx , core -> wrapbase + BCMA_IOCTL ,
494465 postreset | BCMA_IOCTL_CLK );
495466 ci -> ops -> read32 (ci -> ctx , core -> wrapbase + BCMA_IOCTL );
496-
497- if (d11priv2 ) {
498- ci -> ops -> write32 (ci -> ctx , d11priv2 -> wrapbase + BCMA_IOCTL ,
499- postreset | BCMA_IOCTL_CLK );
500- ci -> ops -> read32 (ci -> ctx , d11priv2 -> wrapbase + BCMA_IOCTL );
501- }
502467}
503468
504469char * brcmf_chip_name (u32 id , u32 rev , char * buf , uint len )
@@ -1354,14 +1319,15 @@ static inline void
13541319brcmf_chip_ca7_set_passive (struct brcmf_chip_priv * chip )
13551320{
13561321 struct brcmf_core * core ;
1322+ int i ;
13571323
13581324 brcmf_chip_disable_arm (chip , BCMA_CORE_ARM_CA7 );
13591325
1360- core = brcmf_chip_get_core ( & chip -> pub , BCMA_CORE_80211 );
1361- brcmf_chip_resetcore ( core , D11_BCMA_IOCTL_PHYRESET |
1362- D11_BCMA_IOCTL_PHYCLOCKEN ,
1363- D11_BCMA_IOCTL_PHYCLOCKEN ,
1364- D11_BCMA_IOCTL_PHYCLOCKEN );
1326+ /* Disable the cores only and let the firmware enable them. */
1327+ for ( i = 0 ; ( core = brcmf_chip_get_d11core ( & chip -> pub , i )); i ++ )
1328+ brcmf_chip_coredisable ( core , D11_BCMA_IOCTL_PHYRESET |
1329+ D11_BCMA_IOCTL_PHYCLOCKEN ,
1330+ D11_BCMA_IOCTL_PHYCLOCKEN );
13651331}
13661332
13671333static bool brcmf_chip_ca7_set_active (struct brcmf_chip_priv * chip , u32 rstvec )
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