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torvaldstorvalds
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Merge tag 'drm-fixes-2024-03-01' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie: "Bunch of fixes, xe, amdgpu, nouveau and tegra all have a few. Then drm/bridge including some drivers/soc fallout fixes. The biggest thing in here is a new unit test for some buddy allocator fixes, otherwise a misc fbcon, ttm unit test and one msm revert. Seems pretty normal for this stage. buddy: - two allocation fixes + unit test fbcon: - font restore syzkaller fix ttm: - kunit test fix bridge: - fix aux-hpd leaks - fix aux-hpd registration - fix use after free in soc/qcom - fix boot on soc/qcom xe: - A couple of tracepoint updates from Priyanka and Lucas - Make sure BINDs are completed before accepting UNBINDs on LR vms - Don't arbitrarily restrict max number of batched binds - Add uapi for dumpable bos (agreed on IRC) - Remove unused uapi flags and a leftover comment - A couple of fixes related to the execlist backend msm: - DP: Revert a change which was causing a HDP regression amdgpu: - Fix potential buffer overflow - Fix power min cap - Suspend/resume fix - SI PM fix - eDP fix nouveau: - fix a misreported VRAM sizing - fix a regression in suspend/resume due to freeing tegra: - host1x reset fix - only remove existing driver if display is possible" * tag 'drm-fixes-2024-03-01' of https://gitlab.freedesktop.org/drm/kernel: (32 commits) drm/nouveau: keep DMA buffers required for suspend/resume nouveau: report byte usage in VRAM usage drm/xe/xe_trace: Add move_lacks_source detail to xe_bo_move trace drm/xe: Deny unbinds if uapi ufence pending drm/xe: Expose user fence from xe_sync_entry drm/xe: Use pointers in trace events drm/xe/xe_bo_move: Enhance xe_bo_move trace drm/xe/mmio: fix build warning for BAR resize on 32-bit drm/xe: get rid of MAX_BINDS drm/xe: Use vmalloc for array of bind allocation in bind IOCTL drm/xe: Don't support execlists in xe_gt_tlb_invalidation layer drm/xe: Fix execlist splat drm/xe/uapi: Remove unused flags drm/xe/uapi: Remove DRM_XE_VM_BIND_FLAG_ASYNC comment left over drm/xe: Add uapi for dumpable bos drm/amd/display: Add monitor patch for specific eDP Revert "drm/msm/dp: use drm_bridge_hpd_notify() to report HPD status changes" drm/tests/drm_buddy: add alloc_range_bias test drm/buddy: check range allocation matches alignment drm/buddy: fix range bias ...
2 parents 161671a + f6ecfda commit 7187ea0

39 files changed

Lines changed: 659 additions & 293 deletions

‎drivers/gpu/drm/Kconfig‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -199,15 +199,16 @@ config DRM_TTM
199199
config DRM_TTM_KUNIT_TEST
200200
tristate "KUnit tests for TTM" if !KUNIT_ALL_TESTS
201201
default n
202-
depends on DRM && KUNIT && MMU
202+
depends on DRM && KUNIT && MMU && (UML || COMPILE_TEST)
203203
select DRM_TTM
204204
select DRM_EXPORT_FOR_TESTS if m
205205
select DRM_KUNIT_TEST_HELPERS
206206
default KUNIT_ALL_TESTS
207207
help
208208
Enables unit tests for TTM, a GPU memory manager subsystem used
209209
to manage memory buffers. This option is mostly useful for kernel
210-
developers.
210+
developers. It depends on (UML || COMPILE_TEST) since no other driver
211+
which uses TTM can be loaded while running the tests.
211212

212213
If in doubt, say "N".
213214

‎drivers/gpu/drm/amd/amdgpu/soc15.c‎

Lines changed: 25 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -574,11 +574,34 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
574574
return AMD_RESET_METHOD_MODE1;
575575
}
576576

577+
static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
578+
{
579+
u32 sol_reg;
580+
581+
sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
582+
583+
/* Will reset for the following suspend abort cases.
584+
* 1) Only reset limit on APU side, dGPU hasn't checked yet.
585+
* 2) S3 suspend abort and TOS already launched.
586+
*/
587+
if (adev->flags & AMD_IS_APU && adev->in_s3 &&
588+
!adev->suspend_complete &&
589+
sol_reg)
590+
return true;
591+
592+
return false;
593+
}
594+
577595
static int soc15_asic_reset(struct amdgpu_device *adev)
578596
{
579597
/* original raven doesn't have full asic reset */
580-
if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
581-
(adev->apu_flags & AMD_APU_IS_RAVEN2))
598+
/* On the latest Raven, the GPU reset can be performed
599+
* successfully. So now, temporarily enable it for the
600+
* S3 suspend abort case.
601+
*/
602+
if (((adev->apu_flags & AMD_APU_IS_RAVEN) ||
603+
(adev->apu_flags & AMD_APU_IS_RAVEN2)) &&
604+
!soc15_need_reset_on_resume(adev))
582605
return 0;
583606

584607
switch (soc15_asic_reset_method(adev)) {
@@ -1298,24 +1321,6 @@ static int soc15_common_suspend(void *handle)
12981321
return soc15_common_hw_fini(adev);
12991322
}
13001323

1301-
static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
1302-
{
1303-
u32 sol_reg;
1304-
1305-
sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1306-
1307-
/* Will reset for the following suspend abort cases.
1308-
* 1) Only reset limit on APU side, dGPU hasn't checked yet.
1309-
* 2) S3 suspend abort and TOS already launched.
1310-
*/
1311-
if (adev->flags & AMD_IS_APU && adev->in_s3 &&
1312-
!adev->suspend_complete &&
1313-
sol_reg)
1314-
return true;
1315-
1316-
return false;
1317-
}
1318-
13191324
static int soc15_common_resume(void *handle)
13201325
{
13211326
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,8 @@ static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps)
6767
/* Workaround for some monitors that do not clear DPCD 0x317 if FreeSync is unsupported */
6868
case drm_edid_encode_panel_id('A', 'U', 'O', 0xA7AB):
6969
case drm_edid_encode_panel_id('A', 'U', 'O', 0xE69B):
70+
case drm_edid_encode_panel_id('B', 'O', 'E', 0x092A):
71+
case drm_edid_encode_panel_id('L', 'G', 'D', 0x06D1):
7072
DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id);
7173
edid_caps->panel_patch.remove_sink_ext_caps = true;
7274
break;
@@ -120,6 +122,8 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
120122

121123
edid_caps->edid_hdmi = connector->display_info.is_hdmi;
122124

125+
apply_edid_quirks(edid_buf, edid_caps);
126+
123127
sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
124128
if (sad_count <= 0)
125129
return result;
@@ -146,8 +150,6 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
146150
else
147151
edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
148152

149-
apply_edid_quirks(edid_buf, edid_caps);
150-
151153
kfree(sads);
152154
kfree(sadb);
153155

‎drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,11 @@ static void map_hw_resources(struct dml2_context *dml2,
7676
in_out_display_cfg->hw.DLGRefClkFreqMHz = 50;
7777
}
7878
for (j = 0; j < mode_support_info->DPPPerSurface[i]; j++) {
79+
if (i >= __DML2_WRAPPER_MAX_STREAMS_PLANES__) {
80+
dml_print("DML::%s: Index out of bounds: i=%d, __DML2_WRAPPER_MAX_STREAMS_PLANES__=%d\n",
81+
__func__, i, __DML2_WRAPPER_MAX_STREAMS_PLANES__);
82+
break;
83+
}
7984
dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i];
8085
dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[num_pipes] = true;
8186
dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i];

‎drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6925,6 +6925,23 @@ static int si_dpm_enable(struct amdgpu_device *adev)
69256925
return 0;
69266926
}
69276927

6928+
static int si_set_temperature_range(struct amdgpu_device *adev)
6929+
{
6930+
int ret;
6931+
6932+
ret = si_thermal_enable_alert(adev, false);
6933+
if (ret)
6934+
return ret;
6935+
ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6936+
if (ret)
6937+
return ret;
6938+
ret = si_thermal_enable_alert(adev, true);
6939+
if (ret)
6940+
return ret;
6941+
6942+
return ret;
6943+
}
6944+
69286945
static void si_dpm_disable(struct amdgpu_device *adev)
69296946
{
69306947
struct rv7xx_power_info *pi = rv770_get_pi(adev);
@@ -7608,6 +7625,18 @@ static int si_dpm_process_interrupt(struct amdgpu_device *adev,
76087625

76097626
static int si_dpm_late_init(void *handle)
76107627
{
7628+
int ret;
7629+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7630+
7631+
if (!adev->pm.dpm_enabled)
7632+
return 0;
7633+
7634+
ret = si_set_temperature_range(adev);
7635+
if (ret)
7636+
return ret;
7637+
#if 0 //TODO ?
7638+
si_dpm_powergate_uvd(adev, true);
7639+
#endif
76117640
return 0;
76127641
}
76137642

‎drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1303,13 +1303,12 @@ static int arcturus_get_power_limit(struct smu_context *smu,
13031303
if (default_power_limit)
13041304
*default_power_limit = power_limit;
13051305

1306-
if (smu->od_enabled) {
1306+
if (smu->od_enabled)
13071307
od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1308-
od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1309-
} else {
1308+
else
13101309
od_percent_upper = 0;
1311-
od_percent_lower = 100;
1312-
}
1310+
1311+
od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
13131312

13141313
dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
13151314
od_percent_upper, od_percent_lower, power_limit);

‎drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2357,13 +2357,12 @@ static int navi10_get_power_limit(struct smu_context *smu,
23572357
*default_power_limit = power_limit;
23582358

23592359
if (smu->od_enabled &&
2360-
navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
2360+
navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT))
23612361
od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
2362-
od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
2363-
} else {
2362+
else
23642363
od_percent_upper = 0;
2365-
od_percent_lower = 100;
2366-
}
2364+
2365+
od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
23672366

23682367
dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
23692368
od_percent_upper, od_percent_lower, power_limit);

‎drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -640,13 +640,12 @@ static int sienna_cichlid_get_power_limit(struct smu_context *smu,
640640
if (default_power_limit)
641641
*default_power_limit = power_limit;
642642

643-
if (smu->od_enabled) {
643+
if (smu->od_enabled)
644644
od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
645-
od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
646-
} else {
645+
else
647646
od_percent_upper = 0;
648-
od_percent_lower = 100;
649-
}
647+
648+
od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
650649

651650
dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
652651
od_percent_upper, od_percent_lower, power_limit);

‎drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2369,13 +2369,12 @@ static int smu_v13_0_0_get_power_limit(struct smu_context *smu,
23692369
if (default_power_limit)
23702370
*default_power_limit = power_limit;
23712371

2372-
if (smu->od_enabled) {
2372+
if (smu->od_enabled)
23732373
od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
2374-
od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
2375-
} else {
2374+
else
23762375
od_percent_upper = 0;
2377-
od_percent_lower = 100;
2378-
}
2376+
2377+
od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
23792378

23802379
dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
23812380
od_percent_upper, od_percent_lower, power_limit);

‎drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2333,13 +2333,12 @@ static int smu_v13_0_7_get_power_limit(struct smu_context *smu,
23332333
if (default_power_limit)
23342334
*default_power_limit = power_limit;
23352335

2336-
if (smu->od_enabled) {
2336+
if (smu->od_enabled)
23372337
od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
2338-
od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
2339-
} else {
2338+
else
23402339
od_percent_upper = 0;
2341-
od_percent_lower = 100;
2342-
}
2340+
2341+
od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
23432342

23442343
dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
23452344
od_percent_upper, od_percent_lower, power_limit);

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