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chleroympe
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powerpc: Remove core support for 40x
Now that 40x platforms have gone, remove support for 40x in the core of powerpc arch. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20240628121201.130802-4-mpe@ellerman.id.au
1 parent e939da8 commit 732b32d

29 files changed

Lines changed: 14 additions & 1728 deletions

arch/powerpc/include/asm/cputable.h

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -353,7 +353,6 @@ static inline void cpu_feature_keys_init(void) { }
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CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE | CPU_FTR_NOEXECUTE)
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#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON)
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#define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE)
356-
#define CPU_FTRS_40X (CPU_FTR_NOEXECUTE)
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#define CPU_FTRS_44X (CPU_FTR_NOEXECUTE)
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#define CPU_FTRS_440x6 (CPU_FTR_NOEXECUTE | \
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CPU_FTR_INDEXED_DCR)
@@ -507,9 +506,6 @@ enum {
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#ifdef CONFIG_PPC_8xx
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CPU_FTRS_8XX |
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#endif
510-
#ifdef CONFIG_40x
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CPU_FTRS_40X |
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#endif
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#ifdef CONFIG_PPC_47x
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CPU_FTRS_47X | CPU_FTR_476_DD2 |
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#elif defined(CONFIG_44x)
@@ -582,9 +578,6 @@ enum {
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#ifdef CONFIG_PPC_8xx
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CPU_FTRS_8XX &
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#endif
585-
#ifdef CONFIG_40x
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CPU_FTRS_40X &
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#endif
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#ifdef CONFIG_PPC_47x
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CPU_FTRS_47X &
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#elif defined(CONFIG_44x)

arch/powerpc/include/asm/mmu.h

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Original file line numberDiff line numberDiff line change
@@ -16,7 +16,6 @@
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*/
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#define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
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#define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
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#define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
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#define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
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#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
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#define MMU_FTR_TYPE_47x ASM_CONST(0x00000020)
@@ -153,9 +152,6 @@ enum {
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#ifdef CONFIG_PPC_8xx
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MMU_FTR_TYPE_8xx |
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#endif
156-
#ifdef CONFIG_40x
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MMU_FTR_TYPE_40x |
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#endif
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#ifdef CONFIG_PPC_47x
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MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL |
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#elif defined(CONFIG_44x)
@@ -202,9 +198,6 @@ enum {
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#ifdef CONFIG_PPC_8xx
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#define MMU_FTRS_ALWAYS MMU_FTR_TYPE_8xx
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#endif
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#ifdef CONFIG_40x
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#define MMU_FTRS_ALWAYS MMU_FTR_TYPE_40x
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#endif
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#ifdef CONFIG_PPC_47x
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#define MMU_FTRS_ALWAYS MMU_FTR_TYPE_47x
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#elif defined(CONFIG_44x)

arch/powerpc/include/asm/nohash/32/mmu-40x.h

Lines changed: 0 additions & 68 deletions
This file was deleted.

arch/powerpc/include/asm/nohash/32/pgtable.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -118,9 +118,7 @@
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* (hardware-defined) PowerPC PTE as closely as possible.
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*/
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121-
#if defined(CONFIG_40x)
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#include <asm/nohash/32/pte-40x.h>
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#elif defined(CONFIG_44x)
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#if defined(CONFIG_44x)
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#include <asm/nohash/32/pte-44x.h>
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#elif defined(CONFIG_PPC_85xx) && defined(CONFIG_PTE_64BIT)
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#include <asm/nohash/pte-e500.h>

arch/powerpc/include/asm/nohash/32/pte-40x.h

Lines changed: 0 additions & 73 deletions
This file was deleted.

arch/powerpc/include/asm/nohash/mmu.h

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Original file line numberDiff line numberDiff line change
@@ -2,10 +2,7 @@
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#ifndef _ASM_POWERPC_NOHASH_MMU_H_
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#define _ASM_POWERPC_NOHASH_MMU_H_
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5-
#if defined(CONFIG_40x)
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/* 40x-style software loaded TLB */
7-
#include <asm/nohash/32/mmu-40x.h>
8-
#elif defined(CONFIG_44x)
5+
#if defined(CONFIG_44x)
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/* 44x-style software loaded TLB */
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#include <asm/nohash/32/mmu-44x.h>
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#elif defined(CONFIG_PPC_E500)

arch/powerpc/include/asm/reg.h

Lines changed: 1 addition & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -233,14 +233,10 @@
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/* Special Purpose Registers (SPRNs)*/
235235

236-
#ifdef CONFIG_40x
237-
#define SPRN_PID 0x3B1 /* Process ID */
238-
#else
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#define SPRN_PID 0x030 /* Process ID */
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#ifdef CONFIG_BOOKE
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#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
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#endif
243-
#endif
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#define SPRN_CTR 0x009 /* Count Register */
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#define SPRN_DSCR 0x11
@@ -527,7 +523,7 @@
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#define SPRN_TSCR 0x399 /* Thread Switch Control Register */
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#define SPRN_DEC 0x016 /* Decrement Register */
530-
#define SPRN_PIT 0x3DB /* Programmable Interval Timer (40x/BOOKE) */
526+
#define SPRN_PIT 0x3DB /* Programmable Interval Timer (BOOKE) */
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#define SPRN_DER 0x095 /* Debug Enable Register */
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#define DER_RSTE 0x40000000 /* Reset Interrupt */
@@ -1116,15 +1112,6 @@
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* - SPRG2 indicator that we are in RTAS
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* - SPRG4 (603 only) pseudo TLB LRU data
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*
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* 32-bit 40x:
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* - SPRG0 scratch for exception vectors
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* - SPRG1 scratch for exception vectors
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* - SPRG2 scratch for exception vectors
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* - SPRG4 scratch for exception vectors (not 403)
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* - SPRG5 scratch for exception vectors (not 403)
1125-
* - SPRG6 scratch for exception vectors (not 403)
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* - SPRG7 scratch for exception vectors (not 403)
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*
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* 32-bit 440 and FSL BookE:
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* - SPRG0 scratch for exception vectors
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* - SPRG1 scratch for exception vectors (*)
@@ -1216,16 +1203,6 @@
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#define SPRN_SPRG_603_LRU SPRN_SPRG4
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#endif
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1219-
#ifdef CONFIG_40x
1220-
#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1221-
#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1222-
#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
1223-
#define SPRN_SPRG_SCRATCH3 SPRN_SPRG4
1224-
#define SPRN_SPRG_SCRATCH4 SPRN_SPRG5
1225-
#define SPRN_SPRG_SCRATCH5 SPRN_SPRG6
1226-
#define SPRN_SPRG_SCRATCH6 SPRN_SPRG7
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#endif
1228-
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#ifdef CONFIG_BOOKE
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#define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0
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#define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0

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