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aford173vinodkoul
aford173
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phy: freescale: fsl-samsung-hdmi: Remove unnecessary LUT entries
The lookup table contains entries which use the integer divider instead of just the fractional divider. Since the set and round functions check both the integer divider values and the LUT values, it's no longer necessary to keep the integer divider values in the lookup table, as can be dynamically calcuated. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Link: https://lore.kernel.org/r/20240914112816.520224-6-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Lines changed: 13 additions & 70 deletions

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‎drivers/phy/freescale/phy-fsl-samsung-hdmi.c‎

Lines changed: 13 additions & 70 deletions
Original file line numberDiff line numberDiff line change
@@ -69,25 +69,16 @@ static const struct phy_config phy_pll_cfg[] = {
6969
}, {
7070
.pixclk = 23750000,
7171
.pll_div_regs = { 0xd1, 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 },
72-
}, {
73-
.pixclk = 24000000,
74-
.pll_div_regs = { 0xd1, 0x50, 0xf0, 0x00, 0x00, 0x80, 0x00 },
7572
}, {
7673
.pixclk = 24024000,
7774
.pll_div_regs = { 0xd1, 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 },
7875
}, {
7976
.pixclk = 25175000,
8077
.pll_div_regs = { 0xd1, 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 },
81-
}, {
82-
.pixclk = 25200000,
83-
.pll_div_regs = { 0xd1, 0x54, 0xf0, 0x00, 0x00, 0x80, 0x00 },
84-
}, {
78+
}, {
8579
.pixclk = 26750000,
8680
.pll_div_regs = { 0xd1, 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 },
87-
}, {
88-
.pixclk = 27000000,
89-
.pll_div_regs = { 0xd1, 0x5a, 0xf0, 0x00, 0x00, 0x80, 0x00 },
90-
}, {
81+
}, {
9182
.pixclk = 27027000,
9283
.pll_div_regs = { 0xd1, 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 },
9384
}, {
@@ -105,18 +96,9 @@ static const struct phy_config phy_pll_cfg[] = {
10596
}, {
10697
.pixclk = 35000000,
10798
.pll_div_regs = { 0xd1, 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 },
108-
}, {
109-
.pixclk = 36000000,
110-
.pll_div_regs = { 0xd1, 0x5a, 0xb0, 0x00, 0x00, 0x80, 0x00 },
111-
}, {
99+
}, {
112100
.pixclk = 36036000,
113101
.pll_div_regs = { 0xd1, 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 },
114-
}, {
115-
.pixclk = 40000000,
116-
.pll_div_regs = { 0xd1, 0x64, 0xb0, 0x00, 0x00, 0x80, 0x00 },
117-
}, {
118-
.pixclk = 43200000,
119-
.pll_div_regs = { 0xd1, 0x5a, 0x90, 0x00, 0x00, 0x80, 0x00 },
120102
}, {
121103
.pixclk = 43243200,
122104
.pll_div_regs = { 0xd1, 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 },
@@ -132,19 +114,13 @@ static const struct phy_config phy_pll_cfg[] = {
132114
}, {
133115
.pixclk = 50349650,
134116
.pll_div_regs = { 0xd1, 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 },
135-
}, {
136-
.pixclk = 50400000,
137-
.pll_div_regs = { 0xd1, 0x54, 0x70, 0x00, 0x00, 0x80, 0x00 },
138117
}, {
139118
.pixclk = 53250000,
140119
.pll_div_regs = { 0xd1, 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 },
141120
}, {
142121
.pixclk = 53500000,
143122
.pll_div_regs = { 0xd1, 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 },
144-
}, {
145-
.pixclk = 54000000,
146-
.pll_div_regs = { 0xd1, 0x5a, 0x70, 0x00, 0x00, 0x80, 0x00 },
147-
}, {
123+
}, {
148124
.pixclk = 54054000,
149125
.pll_div_regs = { 0xd1, 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 },
150126
}, {
@@ -153,10 +129,7 @@ static const struct phy_config phy_pll_cfg[] = {
153129
}, {
154130
.pixclk = 59340659,
155131
.pll_div_regs = { 0xd1, 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 },
156-
}, {
157-
.pixclk = 59400000,
158-
.pll_div_regs = { 0xd1, 0x63, 0x70, 0x00, 0x00, 0x80, 0x00 },
159-
}, {
132+
}, {
160133
.pixclk = 61500000,
161134
.pll_div_regs = { 0xd1, 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 },
162135
}, {
@@ -168,10 +141,7 @@ static const struct phy_config phy_pll_cfg[] = {
168141
}, {
169142
.pixclk = 70000000,
170143
.pll_div_regs = { 0xd1, 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 },
171-
}, {
172-
.pixclk = 72000000,
173-
.pll_div_regs = { 0xd1, 0x5a, 0x50, 0x00, 0x00, 0x80, 0x00 },
174-
}, {
144+
}, {
175145
.pixclk = 72072000,
176146
.pll_div_regs = { 0xd1, 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 },
177147
}, {
@@ -183,10 +153,7 @@ static const struct phy_config phy_pll_cfg[] = {
183153
}, {
184154
.pixclk = 78500000,
185155
.pll_div_regs = { 0xd1, 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 },
186-
}, {
187-
.pixclk = 80000000,
188-
.pll_div_regs = { 0xd1, 0x64, 0x50, 0x00, 0x00, 0x80, 0x00 },
189-
}, {
156+
}, {
190157
.pixclk = 82000000,
191158
.pll_div_regs = { 0xd1, 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 },
192159
}, {
@@ -213,10 +180,7 @@ static const struct phy_config phy_pll_cfg[] = {
213180
}, {
214181
.pixclk = 100699300,
215182
.pll_div_regs = { 0xd1, 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 },
216-
}, {
217-
.pixclk = 100800000,
218-
.pll_div_regs = { 0xd1, 0x54, 0x30, 0x00, 0x00, 0x80, 0x00 },
219-
}, {
183+
}, {
220184
.pixclk = 102500000,
221185
.pll_div_regs = { 0xd1, 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b },
222186
}, {
@@ -228,19 +192,13 @@ static const struct phy_config phy_pll_cfg[] = {
228192
}, {
229193
.pixclk = 107000000,
230194
.pll_div_regs = { 0xd1, 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 },
231-
}, {
232-
.pixclk = 108000000,
233-
.pll_div_regs = { 0xd1, 0x5a, 0x30, 0x00, 0x00, 0x80, 0x00 },
234-
}, {
195+
}, {
235196
.pixclk = 108108000,
236197
.pll_div_regs = { 0xd1, 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 },
237198
}, {
238199
.pixclk = 118000000,
239200
.pll_div_regs = { 0xd1, 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 },
240-
}, {
241-
.pixclk = 118800000,
242-
.pll_div_regs = { 0xd1, 0x63, 0x30, 0x00, 0x00, 0x80, 0x00 },
243-
}, {
201+
}, {
244202
.pixclk = 123000000,
245203
.pll_div_regs = { 0xd1, 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 },
246204
}, {
@@ -261,10 +219,7 @@ static const struct phy_config phy_pll_cfg[] = {
261219
}, {
262220
.pixclk = 140000000,
263221
.pll_div_regs = { 0xd1, 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 },
264-
}, {
265-
.pixclk = 144000000,
266-
.pll_div_regs = { 0xd1, 0x78, 0x30, 0x00, 0x00, 0x80, 0x00 },
267-
}, {
222+
}, {
268223
.pixclk = 148352000,
269224
.pll_div_regs = { 0xd1, 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 },
270225
}, {
@@ -288,9 +243,6 @@ static const struct phy_config phy_pll_cfg[] = {
288243
}, {
289244
.pixclk = 165000000,
290245
.pll_div_regs = { 0xd1, 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b },
291-
}, {
292-
.pixclk = 180000000,
293-
.pll_div_regs = { 0xd1, 0x4b, 0x10, 0x00, 0x00, 0x80, 0x00 },
294246
}, {
295247
.pixclk = 185625000,
296248
.pll_div_regs = { 0xd1, 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 },
@@ -309,25 +261,16 @@ static const struct phy_config phy_pll_cfg[] = {
309261
}, {
310262
.pixclk = 213000000,
311263
.pll_div_regs = { 0xd1, 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 },
312-
}, {
313-
.pixclk = 216000000,
314-
.pll_div_regs = { 0xd1, 0x5a, 0x10, 0x00, 0x00, 0x80, 0x00 },
315264
}, {
316265
.pixclk = 216216000,
317266
.pll_div_regs = { 0xd1, 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 },
318-
}, {
319-
.pixclk = 237600000,
320-
.pll_div_regs = { 0xd1, 0x63, 0x10, 0x00, 0x00, 0x80, 0x00 },
321-
}, {
267+
}, {
322268
.pixclk = 254000000,
323269
.pll_div_regs = { 0xd1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 },
324270
}, {
325271
.pixclk = 277500000,
326272
.pll_div_regs = { 0xd1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d },
327-
}, {
328-
.pixclk = 288000000,
329-
.pll_div_regs = { 0xd1, 0x78, 0x10, 0x00, 0x00, 0x80, 0x00 },
330-
}, {
273+
}, {
331274
.pixclk = 297000000,
332275
.pll_div_regs = { 0xd1, 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 },
333276
},

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