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5 | 5 | #include <linux/platform_device.h> |
6 | 6 | #include <linux/types.h> |
7 | 7 |
|
8 | | -/* tmio MMC platform flags */ |
| 8 | +/* TMIO MMC platform flags */ |
| 9 | + |
9 | 10 | /* |
10 | | - * Some controllers can support a 2-byte block size when the bus width |
11 | | - * is configured in 4-bit mode. |
| 11 | + * Some controllers can support a 2-byte block size when the bus width is |
| 12 | + * configured in 4-bit mode. |
12 | 13 | */ |
13 | 14 | #define TMIO_MMC_BLKSZ_2BYTES BIT(1) |
14 | | -/* |
15 | | - * Some controllers can support SDIO IRQ signalling. |
16 | | - */ |
| 15 | + |
| 16 | +/* Some controllers can support SDIO IRQ signalling */ |
17 | 17 | #define TMIO_MMC_SDIO_IRQ BIT(2) |
18 | 18 |
|
19 | 19 | /* Some features are only available or tested on R-Car Gen2 or later */ |
20 | 20 | #define TMIO_MMC_MIN_RCAR2 BIT(3) |
21 | 21 |
|
22 | 22 | /* |
23 | | - * Some controllers require waiting for the SD bus to become |
24 | | - * idle before writing to some registers. |
| 23 | + * Some controllers require waiting for the SD bus to become idle before |
| 24 | + * writing to some registers. |
25 | 25 | */ |
26 | 26 | #define TMIO_MMC_HAS_IDLE_WAIT BIT(4) |
27 | 27 |
|
|
32 | 32 | */ |
33 | 33 | #define TMIO_MMC_USE_BUSY_TIMEOUT BIT(5) |
34 | 34 |
|
35 | | -/* |
36 | | - * Some controllers have CMD12 automatically |
37 | | - * issue/non-issue register |
38 | | - */ |
| 35 | +/* Some controllers have CMD12 automatically issue/non-issue register */ |
39 | 36 | #define TMIO_MMC_HAVE_CMD12_CTRL BIT(7) |
40 | 37 |
|
41 | 38 | /* Controller has some SDIO status bits which must be 1 */ |
42 | 39 | #define TMIO_MMC_SDIO_STATUS_SETBITS BIT(8) |
43 | 40 |
|
44 | | -/* |
45 | | - * Some controllers have a 32-bit wide data port register |
46 | | - */ |
| 41 | +/* Some controllers have a 32-bit wide data port register */ |
47 | 42 | #define TMIO_MMC_32BIT_DATA_PORT BIT(9) |
48 | 43 |
|
49 | | -/* |
50 | | - * Some controllers allows to set SDx actual clock |
51 | | - */ |
| 44 | +/* Some controllers allows to set SDx actual clock */ |
52 | 45 | #define TMIO_MMC_CLK_ACTUAL BIT(10) |
53 | 46 |
|
54 | 47 | /* Some controllers have a CBSY bit */ |
55 | 48 | #define TMIO_MMC_HAVE_CBSY BIT(11) |
56 | 49 |
|
57 | | -/* |
58 | | - * data for the MMC controller |
59 | | - */ |
60 | 50 | struct tmio_mmc_data { |
61 | 51 | void *chan_priv_tx; |
62 | 52 | void *chan_priv_rx; |
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