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perf vendor events intel: Update pantherlake events from 1.00 to 1.02
The updated events were published in: intel/perfmon@6edacf4 Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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‎tools/perf/pmu-events/arch/x86/mapfile.csv‎

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@@ -26,7 +26,7 @@ GenuineIntel-6-BD,v1.19,lunarlake,core
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GenuineIntel-6-(AA|AC|B5),v1.18,meteorlake,core
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GenuineIntel-6-1[AEF],v4,nehalemep,core
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GenuineIntel-6-2E,v4,nehalemex,core
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GenuineIntel-6-CC,v1.00,pantherlake,core
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GenuineIntel-6-CC,v1.02,pantherlake,core
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GenuineIntel-6-A7,v1.04,rocketlake,core
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GenuineIntel-6-2A,v19,sandybridge,core
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GenuineIntel-6-8F,v1.35,sapphirerapids,core

‎tools/perf/pmu-events/arch/x86/pantherlake/cache.json‎

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@@ -383,6 +383,15 @@
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"UMask": "0x10",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the caches, a snoop was required, and hits in other core or module on same die. Another core provides the data with a fwd, no fwd, or hitM.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x34",
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"EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS_OTHERMOD",
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"SampleAfterValue": "1000003",
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"UMask": "0x8",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts all retired load instructions.",
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"Counter": "0,1,2,3",
@@ -727,6 +736,16 @@
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"UMask": "0x40",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and modified data was forwarded.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xd4",
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"EventName": "MEM_LOAD_UOPS_MISC_RETIRED.L3_HIT_SNOOP_HITM",
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"PublicDescription": "Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and modified data was forwarded. Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x8",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of load ops retired that hit the L1 data cache.",
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"Counter": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "100021",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST).",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.ALL",
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"PublicDescription": "Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST). Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x83",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of load ops retired.",
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"Counter": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "100003",
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"UMask": "0x4",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x71",
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"EventName": "TOPDOWN_FE_BOUND.ICACHE",
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"SampleAfterValue": "1000003",
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"UMask": "0x20",
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"Unit": "cpu_atom"
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}
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]

‎tools/perf/pmu-events/arch/x86/pantherlake/floating-point.json‎

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"UMask": "0x3f",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of uops executed on all floating point ports.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xb2",
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"EventName": "FP_VINT_UOPS_EXECUTED.ALL",
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"SampleAfterValue": "1000003",
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"UMask": "0x1f",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xb2",
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"EventName": "FP_VINT_UOPS_EXECUTED.P0",
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"SampleAfterValue": "1000003",
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"UMask": "0x2",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 1.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xb2",
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"EventName": "FP_VINT_UOPS_EXECUTED.P1",
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"SampleAfterValue": "1000003",
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"UMask": "0x4",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 2.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xb2",
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"EventName": "FP_VINT_UOPS_EXECUTED.P2",
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"SampleAfterValue": "1000003",
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"UMask": "0x8",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 3.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xb2",
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"EventName": "FP_VINT_UOPS_EXECUTED.P3",
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"SampleAfterValue": "1000003",
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"UMask": "0x10",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0, 1, 2, 3.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xb2",
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"EventName": "FP_VINT_UOPS_EXECUTED.PRIMARY",
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"SampleAfterValue": "1000003",
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"UMask": "0x1e",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of uops executed on floating point and vector integer store data port.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xb2",
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"EventName": "FP_VINT_UOPS_EXECUTED.STD",
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"SampleAfterValue": "1000003",
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"UMask": "0x1",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
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"Counter": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"UMask": "0x4",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc2",
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"EventName": "UOPS_RETIRED.FPDIV",
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"PublicDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt). Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x40",
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"Unit": "cpu_atom"
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}
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]

‎tools/perf/pmu-events/arch/x86/pantherlake/memory.json‎

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"UMask": "0xf4",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to request buffers full or lock in progress.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x05",
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"EventName": "LD_HEAD.WCB_FULL",
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"SampleAfterValue": "1000003",
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"UMask": "0x2",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
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"Counter": "0,1,2,3,4,5,6,7",

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