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RDMA/irdma: Discover and set up GEN3 hardware register layout
Discover the hardware register layout for GEN3 devices through an RDMA virtual channel operation with the Control Plane (CP). Set up the corresponding hardware attributes specific to GEN3 devices. Signed-off-by: Christopher Bednarz <christopher.n.bednarz@intel.com> Signed-off-by: Tatyana Nikolova <tatyana.e.nikolova@intel.com> Link: https://patch.msgid.link/20250827152545.2056-4-tatyana.e.nikolova@intel.com Tested-by: Jacob Moroni <jmoroni@google.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>
1 parent d5edd33 commit 7d5a7cc

12 files changed

Lines changed: 351 additions & 15 deletions

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‎drivers/infiniband/hw/irdma/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ irdma-objs := cm.o \
1616
ig3rdma_if.o\
1717
icrdma_if.o \
1818
icrdma_hw.o \
19+
ig3rdma_hw.o\
1920
main.o \
2021
pble.o \
2122
puda.o \

‎drivers/infiniband/hw/irdma/ctrl.c‎

Lines changed: 21 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -5672,6 +5672,9 @@ static inline void irdma_sc_init_hw(struct irdma_sc_dev *dev)
56725672
case IRDMA_GEN_2:
56735673
icrdma_init_hw(dev);
56745674
break;
5675+
case IRDMA_GEN_3:
5676+
ig3rdma_init_hw(dev);
5677+
break;
56755678
}
56765679
}
56775680

@@ -5742,18 +5745,26 @@ int irdma_sc_dev_init(enum irdma_vers ver, struct irdma_sc_dev *dev,
57425745

57435746
irdma_sc_init_hw(dev);
57445747

5745-
if (irdma_wait_pe_ready(dev))
5746-
return -ETIMEDOUT;
5748+
if (dev->privileged) {
5749+
if (irdma_wait_pe_ready(dev))
5750+
return -ETIMEDOUT;
57475751

5748-
val = readl(dev->hw_regs[IRDMA_GLPCI_LBARCTRL]);
5749-
db_size = (u8)FIELD_GET(IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE, val);
5750-
if (db_size != IRDMA_PE_DB_SIZE_4M && db_size != IRDMA_PE_DB_SIZE_8M) {
5751-
ibdev_dbg(to_ibdev(dev),
5752-
"DEV: RDMA PE doorbell is not enabled in CSR val 0x%x db_size=%d\n",
5753-
val, db_size);
5754-
return -ENODEV;
5752+
val = readl(dev->hw_regs[IRDMA_GLPCI_LBARCTRL]);
5753+
db_size = (u8)FIELD_GET(IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE, val);
5754+
if (db_size != IRDMA_PE_DB_SIZE_4M &&
5755+
db_size != IRDMA_PE_DB_SIZE_8M) {
5756+
ibdev_dbg(to_ibdev(dev),
5757+
"DEV: RDMA PE doorbell is not enabled in CSR val 0x%x db_size=%d\n",
5758+
val, db_size);
5759+
return -ENODEV;
5760+
}
5761+
} else {
5762+
ret_code = irdma_vchnl_req_get_reg_layout(dev);
5763+
if (ret_code)
5764+
ibdev_dbg(to_ibdev(dev),
5765+
"DEV: Get Register layout failed ret = %d\n",
5766+
ret_code);
57555767
}
5756-
dev->db_addr = dev->hw->hw_addr + (uintptr_t)dev->hw_regs[IRDMA_DB_ADDR_OFFSET];
57575768

57585769
return ret_code;
57595770
}

‎drivers/infiniband/hw/irdma/defs.h‎

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,7 @@ enum irdma_protocol_used {
115115
#define IRDMA_FEATURE_BUF_SIZE (8 * IRDMA_MAX_FEATURES)
116116

117117
#define ENABLE_LOC_MEM 63
118+
#define IRDMA_ATOMICS_ALLOWED_BIT 1
118119
#define MAX_PBLE_PER_SD 0x40000
119120
#define MAX_PBLE_SD_PER_FCN 0x400
120121
#define MAX_MR_PER_SD 0x8000
@@ -127,7 +128,7 @@ enum irdma_protocol_used {
127128
#define IRDMA_QP_SW_MAX_RQ_QUANTA 32768
128129
#define IRDMA_MAX_QP_WRS(max_quanta_per_wr) \
129130
((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
130-
131+
#define IRDMA_SRQ_MAX_QUANTA 262144
131132
#define IRDMAQP_TERM_SEND_TERM_AND_FIN 0
132133
#define IRDMAQP_TERM_SEND_TERM_ONLY 1
133134
#define IRDMAQP_TERM_SEND_FIN_ONLY 2
@@ -153,8 +154,13 @@ enum irdma_protocol_used {
153154
#define IRDMA_SQ_RSVD 258
154155
#define IRDMA_RQ_RSVD 1
155156

156-
#define IRDMA_FEATURE_RTS_AE 1ULL
157-
#define IRDMA_FEATURE_CQ_RESIZE 2ULL
157+
#define IRDMA_FEATURE_RTS_AE BIT_ULL(0)
158+
#define IRDMA_FEATURE_CQ_RESIZE BIT_ULL(1)
159+
#define IRDMA_FEATURE_64_BYTE_CQE BIT_ULL(5)
160+
#define IRDMA_FEATURE_ATOMIC_OPS BIT_ULL(6)
161+
#define IRDMA_FEATURE_SRQ BIT_ULL(7)
162+
#define IRDMA_FEATURE_CQE_TIMESTAMPING BIT_ULL(8)
163+
158164
#define IRDMAQP_OP_RDMA_WRITE 0x00
159165
#define IRDMAQP_OP_RDMA_READ 0x01
160166
#define IRDMAQP_OP_RDMA_SEND 0x03

‎drivers/infiniband/hw/irdma/i40iw_hw.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,7 @@ static u64 i40iw_masks[IRDMA_MAX_MASKS] = {
8585
I40E_CQPSQ_CQ_CEQID,
8686
I40E_CQPSQ_CQ_CQID,
8787
I40E_COMMIT_FPM_CQCNT,
88+
I40E_CQPSQ_UPESD_HMCFNID,
8889
};
8990

9091
static u64 i40iw_shifts[IRDMA_MAX_SHIFTS] = {
@@ -94,6 +95,7 @@ static u64 i40iw_shifts[IRDMA_MAX_SHIFTS] = {
9495
I40E_CQPSQ_CQ_CEQID_S,
9596
I40E_CQPSQ_CQ_CQID_S,
9697
I40E_COMMIT_FPM_CQCNT_S,
98+
I40E_CQPSQ_UPESD_HMCFNID_S,
9799
};
98100

99101
/**

‎drivers/infiniband/hw/irdma/i40iw_hw.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -123,6 +123,8 @@
123123
#define I40E_CQPSQ_CQ_CQID GENMASK_ULL(15, 0)
124124
#define I40E_COMMIT_FPM_CQCNT_S 0
125125
#define I40E_COMMIT_FPM_CQCNT GENMASK_ULL(17, 0)
126+
#define I40E_CQPSQ_UPESD_HMCFNID_S 0
127+
#define I40E_CQPSQ_UPESD_HMCFNID GENMASK_ULL(5, 0)
126128

127129
#define I40E_VSIQF_CTL(_VSI) (0x0020D800 + ((_VSI) * 4))
128130

‎drivers/infiniband/hw/irdma/icrdma_hw.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@ static u64 icrdma_masks[IRDMA_MAX_MASKS] = {
3838
ICRDMA_CQPSQ_CQ_CEQID,
3939
ICRDMA_CQPSQ_CQ_CQID,
4040
ICRDMA_COMMIT_FPM_CQCNT,
41+
ICRDMA_CQPSQ_UPESD_HMCFNID,
4142
};
4243

4344
static u64 icrdma_shifts[IRDMA_MAX_SHIFTS] = {
@@ -47,6 +48,7 @@ static u64 icrdma_shifts[IRDMA_MAX_SHIFTS] = {
4748
ICRDMA_CQPSQ_CQ_CEQID_S,
4849
ICRDMA_CQPSQ_CQ_CQID_S,
4950
ICRDMA_COMMIT_FPM_CQCNT_S,
51+
ICRDMA_CQPSQ_UPESD_HMCFNID_S,
5052
};
5153

5254
/**
@@ -194,6 +196,7 @@ void icrdma_init_hw(struct irdma_sc_dev *dev)
194196
dev->hw_attrs.max_hw_ord = ICRDMA_MAX_ORD_SIZE;
195197
dev->hw_attrs.max_stat_inst = ICRDMA_MAX_STATS_COUNT;
196198
dev->hw_attrs.max_stat_idx = IRDMA_HW_STAT_INDEX_MAX_GEN_2;
199+
dev->hw_attrs.max_hw_device_pages = ICRDMA_MAX_PUSH_PAGE_COUNT;
197200

198201
dev->hw_attrs.uk_attrs.min_hw_wq_size = ICRDMA_MIN_WQ_SIZE;
199202
dev->hw_attrs.uk_attrs.max_hw_sq_chunk = IRDMA_MAX_QUANTA_PER_WR;

‎drivers/infiniband/hw/irdma/icrdma_hw.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -58,14 +58,15 @@
5858
#define ICRDMA_CQPSQ_CQ_CQID GENMASK_ULL(18, 0)
5959
#define ICRDMA_COMMIT_FPM_CQCNT_S 0
6060
#define ICRDMA_COMMIT_FPM_CQCNT GENMASK_ULL(19, 0)
61-
61+
#define ICRDMA_CQPSQ_UPESD_HMCFNID_S 0
62+
#define ICRDMA_CQPSQ_UPESD_HMCFNID GENMASK_ULL(5, 0)
6263
enum icrdma_device_caps_const {
6364
ICRDMA_MAX_STATS_COUNT = 128,
6465

6566
ICRDMA_MAX_IRD_SIZE = 127,
6667
ICRDMA_MAX_ORD_SIZE = 255,
6768
ICRDMA_MIN_WQ_SIZE = 8 /* WQEs */,
68-
69+
ICRDMA_MAX_PUSH_PAGE_COUNT = 256,
6970
};
7071

7172
void icrdma_init_hw(struct irdma_sc_dev *dev);

‎drivers/infiniband/hw/irdma/ig3rdma_hw.c‎

Lines changed: 65 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,65 @@
1+
// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
2+
/* Copyright (c) 2018 - 2024 Intel Corporation */
3+
#include "osdep.h"
4+
#include "type.h"
5+
#include "protos.h"
6+
#include "ig3rdma_hw.h"
7+
8+
void ig3rdma_init_hw(struct irdma_sc_dev *dev)
9+
{
10+
dev->hw_attrs.uk_attrs.hw_rev = IRDMA_GEN_3;
11+
dev->hw_attrs.uk_attrs.max_hw_wq_frags = IG3RDMA_MAX_WQ_FRAGMENT_COUNT;
12+
dev->hw_attrs.uk_attrs.max_hw_read_sges = IG3RDMA_MAX_SGE_RD;
13+
dev->hw_attrs.uk_attrs.max_hw_sq_chunk = IRDMA_MAX_QUANTA_PER_WR;
14+
dev->hw_attrs.first_hw_vf_fpm_id = 0;
15+
dev->hw_attrs.max_hw_vf_fpm_id = IG3_MAX_APFS + IG3_MAX_AVFS;
16+
dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_64_BYTE_CQE;
17+
if (dev->feature_info[IRDMA_FTN_FLAGS] & IRDMA_ATOMICS_ALLOWED_BIT)
18+
dev->hw_attrs.uk_attrs.feature_flags |=
19+
IRDMA_FEATURE_ATOMIC_OPS;
20+
dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_CQE_TIMESTAMPING;
21+
22+
dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_SRQ;
23+
dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_RTS_AE |
24+
IRDMA_FEATURE_CQ_RESIZE;
25+
dev->hw_attrs.page_size_cap = SZ_4K | SZ_2M | SZ_1G;
26+
dev->hw_attrs.max_hw_ird = IG3RDMA_MAX_IRD_SIZE;
27+
dev->hw_attrs.max_hw_ord = IG3RDMA_MAX_ORD_SIZE;
28+
dev->hw_attrs.uk_attrs.min_hw_wq_size = IG3RDMA_MIN_WQ_SIZE;
29+
dev->hw_attrs.uk_attrs.max_hw_srq_quanta = IRDMA_SRQ_MAX_QUANTA;
30+
dev->hw_attrs.uk_attrs.max_hw_inline = IG3RDMA_MAX_INLINE_DATA_SIZE;
31+
dev->hw_attrs.max_hw_device_pages =
32+
dev->is_pf ? IG3RDMA_MAX_PF_PUSH_PAGE_COUNT : IG3RDMA_MAX_VF_PUSH_PAGE_COUNT;
33+
}
34+
35+
static void __iomem *__ig3rdma_get_reg_addr(struct irdma_mmio_region *region, u64 reg_offset)
36+
{
37+
if (reg_offset >= region->offset &&
38+
reg_offset < (region->offset + region->len)) {
39+
reg_offset -= region->offset;
40+
41+
return region->addr + reg_offset;
42+
}
43+
44+
return NULL;
45+
}
46+
47+
void __iomem *ig3rdma_get_reg_addr(struct irdma_hw *hw, u64 reg_offset)
48+
{
49+
u8 __iomem *reg_addr;
50+
int i;
51+
52+
reg_addr = __ig3rdma_get_reg_addr(&hw->rdma_reg, reg_offset);
53+
if (reg_addr)
54+
return reg_addr;
55+
56+
for (i = 0; i < hw->num_io_regions; i++) {
57+
reg_addr = __ig3rdma_get_reg_addr(&hw->io_regs[i], reg_offset);
58+
if (reg_addr)
59+
return reg_addr;
60+
}
61+
62+
WARN_ON_ONCE(1);
63+
64+
return NULL;
65+
}

‎drivers/infiniband/hw/irdma/ig3rdma_hw.h‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,11 +3,29 @@
33
#ifndef IG3RDMA_HW_H
44
#define IG3RDMA_HW_H
55

6+
#define IG3_MAX_APFS 1
7+
#define IG3_MAX_AVFS 0
8+
69
#define IG3_PF_RDMA_REGION_OFFSET 0xBC00000
710
#define IG3_PF_RDMA_REGION_LEN 0x401000
811
#define IG3_VF_RDMA_REGION_OFFSET 0x8C00
912
#define IG3_VF_RDMA_REGION_LEN 0x8400
1013

14+
enum ig3rdma_device_caps_const {
15+
IG3RDMA_MAX_WQ_FRAGMENT_COUNT = 14,
16+
IG3RDMA_MAX_SGE_RD = 14,
17+
18+
IG3RDMA_MAX_STATS_COUNT = 128,
19+
20+
IG3RDMA_MAX_IRD_SIZE = 64,
21+
IG3RDMA_MAX_ORD_SIZE = 64,
22+
IG3RDMA_MIN_WQ_SIZE = 16 /* WQEs */,
23+
IG3RDMA_MAX_INLINE_DATA_SIZE = 216,
24+
IG3RDMA_MAX_PF_PUSH_PAGE_COUNT = 8192,
25+
IG3RDMA_MAX_VF_PUSH_PAGE_COUNT = 16,
26+
};
27+
28+
void __iomem *ig3rdma_get_reg_addr(struct irdma_hw *hw, u64 reg_offset);
1129
int ig3rdma_vchnl_send_sync(struct irdma_sc_dev *dev, u8 *msg, u16 len,
1230
u8 *recv_msg, u16 *recv_len);
1331

‎drivers/infiniband/hw/irdma/irdma.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,7 @@ enum irdma_shifts {
6767
IRDMA_CQPSQ_CQ_CEQID_S,
6868
IRDMA_CQPSQ_CQ_CQID_S,
6969
IRDMA_COMMIT_FPM_CQCNT_S,
70+
IRDMA_CQPSQ_UPESD_HMCFNID_S,
7071
IRDMA_MAX_SHIFTS,
7172
};
7273

@@ -77,6 +78,7 @@ enum irdma_masks {
7778
IRDMA_CQPSQ_CQ_CEQID_M,
7879
IRDMA_CQPSQ_CQ_CQID_M,
7980
IRDMA_COMMIT_FPM_CQCNT_M,
81+
IRDMA_CQPSQ_UPESD_HMCFNID_M,
8082
IRDMA_MAX_MASKS, /* Must be last entry */
8183
};
8284

@@ -121,6 +123,7 @@ struct irdma_uk_attrs {
121123
u32 max_hw_wq_quanta;
122124
u32 min_hw_cq_size;
123125
u32 max_hw_cq_size;
126+
u32 max_hw_srq_quanta;
124127
u16 max_hw_sq_chunk;
125128
u16 min_hw_wq_size;
126129
u8 hw_rev;
@@ -156,4 +159,6 @@ struct irdma_hw_attrs {
156159

157160
void i40iw_init_hw(struct irdma_sc_dev *dev);
158161
void icrdma_init_hw(struct irdma_sc_dev *dev);
162+
void ig3rdma_init_hw(struct irdma_sc_dev *dev);
163+
void __iomem *ig3rdma_get_reg_addr(struct irdma_hw *hw, u64 reg_offset);
159164
#endif /* IRDMA_H*/

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