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Expand file tree Collapse file tree Original file line number Diff line number Diff line change 11121112#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14)
11131113#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
11141114#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
1115- /* AMD-V MSRs */
11161115
1116+ /* AMD-V MSRs */
11171117#define MSR_VM_CR 0xc0010114
11181118#define MSR_VM_IGNNE 0xc0010115
11191119#define MSR_VM_HSAVE_PA 0xc0010117
11201120
1121+ #define SVM_VM_CR_VALID_MASK 0x001fULL
1122+ #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
1123+ #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
1124+
11211125/* Hardware Feedback Interface */
11221126#define MSR_IA32_HW_FEEDBACK_PTR 0x17d0
11231127#define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1
Original file line number Diff line number Diff line change @@ -229,10 +229,6 @@ struct __attribute__ ((__packed__)) vmcb_control_area {
229229#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
230230#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
231231
232- #define SVM_VM_CR_VALID_MASK 0x001fULL
233- #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
234- #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
235-
236232#define SVM_NESTED_CTL_NP_ENABLE BIT(0)
237233#define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
238234#define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2)
@@ -571,8 +567,6 @@ struct vmcb {
571567
572568#define SVM_CPUID_FUNC 0x8000000a
573569
574- #define SVM_VM_CR_SVM_DISABLE 4
575-
576570#define SVM_SELECTOR_S_SHIFT 4
577571#define SVM_SELECTOR_DPL_SHIFT 5
578572#define SVM_SELECTOR_P_SHIFT 7
Original file line number Diff line number Diff line change @@ -1031,6 +1031,8 @@ static void zenbleed_check(struct cpuinfo_x86 *c)
10311031
10321032static void init_amd (struct cpuinfo_x86 * c )
10331033{
1034+ u64 vm_cr ;
1035+
10341036 early_init_amd (c );
10351037
10361038 /*
@@ -1082,6 +1084,14 @@ static void init_amd(struct cpuinfo_x86 *c)
10821084
10831085 init_amd_cacheinfo (c );
10841086
1087+ if (cpu_has (c , X86_FEATURE_SVM )) {
1088+ rdmsrl (MSR_VM_CR , vm_cr );
1089+ if (vm_cr & SVM_VM_CR_SVM_DIS_MASK ) {
1090+ pr_notice_once ("SVM disabled (by BIOS) in MSR_VM_CR\n" );
1091+ clear_cpu_cap (c , X86_FEATURE_SVM );
1092+ }
1093+ }
1094+
10851095 if (!cpu_has (c , X86_FEATURE_LFENCE_RDTSC ) && cpu_has (c , X86_FEATURE_XMM2 )) {
10861096 /*
10871097 * Use LFENCE for execution serialization. On families which
Original file line number Diff line number Diff line change @@ -290,6 +290,8 @@ static void early_init_hygon(struct cpuinfo_x86 *c)
290290
291291static void init_hygon (struct cpuinfo_x86 * c )
292292{
293+ u64 vm_cr ;
294+
293295 early_init_hygon (c );
294296
295297 /*
@@ -320,6 +322,14 @@ static void init_hygon(struct cpuinfo_x86 *c)
320322
321323 init_hygon_cacheinfo (c );
322324
325+ if (cpu_has (c , X86_FEATURE_SVM )) {
326+ rdmsrl (MSR_VM_CR , vm_cr );
327+ if (vm_cr & SVM_VM_CR_SVM_DIS_MASK ) {
328+ pr_notice_once ("SVM disabled (by BIOS) in MSR_VM_CR\n" );
329+ clear_cpu_cap (c , X86_FEATURE_SVM );
330+ }
331+ }
332+
323333 if (cpu_has (c , X86_FEATURE_XMM2 )) {
324334 /*
325335 * Use LFENCE for execution serialization. On families which
Original file line number Diff line number Diff line change @@ -531,8 +531,6 @@ static bool __kvm_is_svm_supported(void)
531531 int cpu = smp_processor_id ();
532532 struct cpuinfo_x86 * c = & cpu_data (cpu );
533533
534- u64 vm_cr ;
535-
536534 if (c -> x86_vendor != X86_VENDOR_AMD &&
537535 c -> x86_vendor != X86_VENDOR_HYGON ) {
538536 pr_err ("CPU %d isn't AMD or Hygon\n" , cpu );
@@ -549,12 +547,6 @@ static bool __kvm_is_svm_supported(void)
549547 return false;
550548 }
551549
552- rdmsrl (MSR_VM_CR , vm_cr );
553- if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE )) {
554- pr_err ("SVM disabled (by BIOS) in MSR_VM_CR on CPU %d\n" , cpu );
555- return false;
556- }
557-
558550 return true;
559551}
560552
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