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Merge branch 'pci/controller/sky1'
- Add module support for platform controller driver (Manikandan K Pillai) - Split headers into 'legacy' (LGA) and 'high perf' (HPA) (Manikandan K Pillai) - Add DT binding and driver for CIX Sky1 (Hans Zhang) * pci/controller/sky1: MAINTAINERS: Add CIX Sky1 PCIe controller driver maintainer PCI: sky1: Add PCIe host support for CIX Sky1 dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings PCI: cadence: Add support for High Perf Architecture (HPA) controller PCI: cadence: Move PCIe RP common functions to a separate file PCI: cadence: Split PCIe controller header file PCI: cadence: Add module support for platform controller driver
2 parents af257c7 + 51f38be commit 80a4441

15 files changed

Lines changed: 1844 additions & 516 deletions

‎Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml‎

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/cix,sky1-pcie-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: CIX Sky1 PCIe Root Complex
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maintainers:
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- Hans Zhang <hans.zhang@cixtech.com>
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description:
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PCIe root complex controller based on the Cadence PCIe core.
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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properties:
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compatible:
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const: cix,sky1-pcie-host
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reg:
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items:
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- description: PCIe controller registers.
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- description: ECAM registers.
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- description: Remote CIX System Unit strap registers.
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- description: Remote CIX System Unit status registers.
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- description: Region for sending messages registers.
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reg-names:
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items:
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- const: reg
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- const: cfg
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- const: rcsu_strap
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- const: rcsu_status
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- const: msg
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ranges:
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maxItems: 3
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required:
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- compatible
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- ranges
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- bus-range
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- device_type
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- interrupt-map
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- interrupt-map-mask
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- msi-map
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@a010000 {
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compatible = "cix,sky1-pcie-host";
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reg = <0x00 0x0a010000 0x00 0x10000>,
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<0x00 0x2c000000 0x00 0x4000000>,
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<0x00 0x0a000300 0x00 0x100>,
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<0x00 0x0a000400 0x00 0x100>,
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<0x00 0x60000000 0x00 0x00100000>;
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reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
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ranges = <0x01000000 0x00 0x60100000 0x00 0x60100000 0x00 0x00100000>,
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<0x02000000 0x00 0x60200000 0x00 0x60200000 0x00 0x1fe00000>,
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<0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>;
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0xc0 0xff>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>,
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<0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>,
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<0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>,
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<0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>;
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msi-map = <0xc000 &gic_its 0xc000 0x4000>;
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};
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};

‎MAINTAINERS‎

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@@ -19630,6 +19630,13 @@ S: Orphan
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F: Documentation/devicetree/bindings/pci/cdns,*
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F: drivers/pci/controller/cadence/*cadence*
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PCI DRIVER FOR CIX Sky1
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M: Hans Zhang <hans.zhang@cixtech.com>
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/cix,sky1-pcie-*.yaml
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F: drivers/pci/controller/cadence/*sky1*
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PCI DRIVER FOR FREESCALE LAYERSCAPE
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M: Minghuan Lian <minghuan.Lian@nxp.com>
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M: Mingkai Hu <mingkai.hu@nxp.com>

‎drivers/pci/controller/cadence/Kconfig‎

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@@ -19,10 +19,10 @@ config PCIE_CADENCE_EP
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select PCIE_CADENCE
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config PCIE_CADENCE_PLAT
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bool
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tristate
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config PCIE_CADENCE_PLAT_HOST
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bool "Cadence platform PCIe controller (host mode)"
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tristate "Cadence platform PCIe controller (host mode)"
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depends on OF
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select PCIE_CADENCE_HOST
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select PCIE_CADENCE_PLAT
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vendors SoCs.
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config PCIE_CADENCE_PLAT_EP
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bool "Cadence platform PCIe controller (endpoint mode)"
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tristate "Cadence platform PCIe controller (endpoint mode)"
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depends on OF
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depends on PCI_ENDPOINT
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select PCIE_CADENCE_EP
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endpoint mode. This PCIe controller may be embedded into many
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different vendors SoCs.
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config PCI_SKY1_HOST
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tristate "CIX SKY1 PCIe controller (host mode)"
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depends on OF && (ARCH_CIX || COMPILE_TEST)
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select PCIE_CADENCE_HOST
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select PCI_ECAM
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help
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Say Y here if you want to support the CIX SKY1 PCIe platform
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controller in host mode. CIX SKY1 PCIe controller uses Cadence
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HPA (High Performance Architecture IP [Second generation of
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Cadence PCIe IP])
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This driver requires Cadence PCIe core infrastructure
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(PCIE_CADENCE_HOST) and hardware platform adaptation layer
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to function.
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config PCIE_SG2042_HOST
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tristate "Sophgo SG2042 PCIe controller (host mode)"
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depends on OF && (ARCH_SOPHGO || COMPILE_TEST)

‎drivers/pci/controller/cadence/Makefile‎

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@@ -1,7 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o
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obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o
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obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o
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pcie-cadence-mod-y := pcie-cadence-hpa.o pcie-cadence.o
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pcie-cadence-host-mod-y := pcie-cadence-host-common.o pcie-cadence-host.o pcie-cadence-host-hpa.o
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pcie-cadence-ep-mod-y := pcie-cadence-ep.o
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obj-$(CONFIG_PCIE_CADENCE) = pcie-cadence-mod.o
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obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host-mod.o
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obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep-mod.o
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obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o
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obj-$(CONFIG_PCI_J721E) += pci-j721e.o
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obj-$(CONFIG_PCIE_SG2042_HOST) += pcie-sg2042.o
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obj-$(CONFIG_PCI_SKY1_HOST) += pci-sky1.o

‎drivers/pci/controller/cadence/pci-sky1.c‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe controller driver for CIX's sky1 SoCs
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*
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* Copyright 2025 Cix Technology Group Co., Ltd.
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* Author: Hans Zhang <hans.zhang@cixtech.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pci.h>
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#include <linux/pci-ecam.h>
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#include <linux/pci_ids.h>
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#include "pcie-cadence.h"
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#include "pcie-cadence-host-common.h"
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#define PCI_VENDOR_ID_CIX 0x1f6c
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#define PCI_DEVICE_ID_CIX_SKY1 0x0001
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#define STRAP_REG(n) ((n) * 0x04)
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#define STATUS_REG(n) ((n) * 0x04)
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#define LINK_TRAINING_ENABLE BIT(0)
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#define LINK_COMPLETE BIT(0)
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#define SKY1_IP_REG_BANK 0x1000
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#define SKY1_IP_CFG_CTRL_REG_BANK 0x4c00
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#define SKY1_IP_AXI_MASTER_COMMON 0xf000
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#define SKY1_AXI_SLAVE 0x9000
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#define SKY1_AXI_MASTER 0xb000
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#define SKY1_AXI_HLS_REGISTERS 0xc000
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#define SKY1_AXI_RAS_REGISTERS 0xe000
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#define SKY1_DTI_REGISTERS 0xd000
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#define IP_REG_I_DBG_STS_0 0x420
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struct sky1_pcie {
40+
struct cdns_pcie *cdns_pcie;
41+
struct cdns_pcie_rc *cdns_pcie_rc;
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struct resource *cfg_res;
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struct resource *msg_res;
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struct pci_config_window *cfg;
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void __iomem *strap_base;
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void __iomem *status_base;
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void __iomem *reg_base;
49+
void __iomem *cfg_base;
50+
void __iomem *msg_base;
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};
52+
53+
static int sky1_pcie_resource_get(struct platform_device *pdev,
54+
struct sky1_pcie *pcie)
55+
{
56+
struct device *dev = &pdev->dev;
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struct resource *res;
58+
void __iomem *base;
59+
60+
base = devm_platform_ioremap_resource_byname(pdev, "reg");
61+
if (IS_ERR(base))
62+
return dev_err_probe(dev, PTR_ERR(base),
63+
"unable to find \"reg\" registers\n");
64+
pcie->reg_base = base;
65+
66+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
67+
if (!res)
68+
return dev_err_probe(dev, -ENODEV, "unable to get \"cfg\" resource\n");
69+
pcie->cfg_res = res;
70+
71+
base = devm_platform_ioremap_resource_byname(pdev, "rcsu_strap");
72+
if (IS_ERR(base))
73+
return dev_err_probe(dev, PTR_ERR(base),
74+
"unable to find \"rcsu_strap\" registers\n");
75+
pcie->strap_base = base;
76+
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base = devm_platform_ioremap_resource_byname(pdev, "rcsu_status");
78+
if (IS_ERR(base))
79+
return dev_err_probe(dev, PTR_ERR(base),
80+
"unable to find \"rcsu_status\" registers\n");
81+
pcie->status_base = base;
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83+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "msg");
84+
if (!res)
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return dev_err_probe(dev, -ENODEV, "unable to get \"msg\" resource\n");
86+
pcie->msg_res = res;
87+
pcie->msg_base = devm_ioremap_resource(dev, res);
88+
if (IS_ERR(pcie->msg_base)) {
89+
return dev_err_probe(dev, PTR_ERR(pcie->msg_base),
90+
"unable to ioremap msg resource\n");
91+
}
92+
93+
return 0;
94+
}
95+
96+
static int sky1_pcie_start_link(struct cdns_pcie *cdns_pcie)
97+
{
98+
struct sky1_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
99+
u32 val;
100+
101+
val = readl(pcie->strap_base + STRAP_REG(1));
102+
val |= LINK_TRAINING_ENABLE;
103+
writel(val, pcie->strap_base + STRAP_REG(1));
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return 0;
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}
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static void sky1_pcie_stop_link(struct cdns_pcie *cdns_pcie)
109+
{
110+
struct sky1_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
111+
u32 val;
112+
113+
val = readl(pcie->strap_base + STRAP_REG(1));
114+
val &= ~LINK_TRAINING_ENABLE;
115+
writel(val, pcie->strap_base + STRAP_REG(1));
116+
}
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static bool sky1_pcie_link_up(struct cdns_pcie *cdns_pcie)
119+
{
120+
u32 val;
121+
122+
val = cdns_pcie_hpa_readl(cdns_pcie, REG_BANK_IP_REG,
123+
IP_REG_I_DBG_STS_0);
124+
return val & LINK_COMPLETE;
125+
}
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127+
static const struct cdns_pcie_ops sky1_pcie_ops = {
128+
.start_link = sky1_pcie_start_link,
129+
.stop_link = sky1_pcie_stop_link,
130+
.link_up = sky1_pcie_link_up,
131+
};
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133+
static int sky1_pcie_probe(struct platform_device *pdev)
134+
{
135+
struct cdns_plat_pcie_of_data *reg_off;
136+
struct device *dev = &pdev->dev;
137+
struct pci_host_bridge *bridge;
138+
struct cdns_pcie *cdns_pcie;
139+
struct resource_entry *bus;
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struct cdns_pcie_rc *rc;
141+
struct sky1_pcie *pcie;
142+
int ret;
143+
144+
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
145+
if (!pcie)
146+
return -ENOMEM;
147+
148+
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
149+
if (!bridge)
150+
return -ENOMEM;
151+
152+
ret = sky1_pcie_resource_get(pdev, pcie);
153+
if (ret < 0)
154+
return ret;
155+
156+
bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
157+
if (!bus)
158+
return -ENODEV;
159+
160+
pcie->cfg = pci_ecam_create(dev, pcie->cfg_res, bus->res,
161+
&pci_generic_ecam_ops);
162+
if (IS_ERR(pcie->cfg))
163+
return PTR_ERR(pcie->cfg);
164+
165+
bridge->ops = (struct pci_ops *)&pci_generic_ecam_ops.pci_ops;
166+
rc = pci_host_bridge_priv(bridge);
167+
rc->ecam_supported = 1;
168+
rc->cfg_base = pcie->cfg->win;
169+
rc->cfg_res = &pcie->cfg->res;
170+
171+
cdns_pcie = &rc->pcie;
172+
cdns_pcie->dev = dev;
173+
cdns_pcie->ops = &sky1_pcie_ops;
174+
cdns_pcie->reg_base = pcie->reg_base;
175+
cdns_pcie->msg_res = pcie->msg_res;
176+
cdns_pcie->is_rc = 1;
177+
178+
reg_off = devm_kzalloc(dev, sizeof(*reg_off), GFP_KERNEL);
179+
if (!reg_off)
180+
return -ENOMEM;
181+
182+
reg_off->ip_reg_bank_offset = SKY1_IP_REG_BANK;
183+
reg_off->ip_cfg_ctrl_reg_offset = SKY1_IP_CFG_CTRL_REG_BANK;
184+
reg_off->axi_mstr_common_offset = SKY1_IP_AXI_MASTER_COMMON;
185+
reg_off->axi_slave_offset = SKY1_AXI_SLAVE;
186+
reg_off->axi_master_offset = SKY1_AXI_MASTER;
187+
reg_off->axi_hls_offset = SKY1_AXI_HLS_REGISTERS;
188+
reg_off->axi_ras_offset = SKY1_AXI_RAS_REGISTERS;
189+
reg_off->axi_dti_offset = SKY1_DTI_REGISTERS;
190+
cdns_pcie->cdns_pcie_reg_offsets = reg_off;
191+
192+
pcie->cdns_pcie = cdns_pcie;
193+
pcie->cdns_pcie_rc = rc;
194+
pcie->cfg_base = rc->cfg_base;
195+
bridge->sysdata = pcie->cfg;
196+
197+
rc->vendor_id = PCI_VENDOR_ID_CIX;
198+
rc->device_id = PCI_DEVICE_ID_CIX_SKY1;
199+
rc->no_inbound_map = 1;
200+
201+
dev_set_drvdata(dev, pcie);
202+
203+
ret = cdns_pcie_hpa_host_setup(rc);
204+
if (ret < 0) {
205+
pci_ecam_free(pcie->cfg);
206+
return ret;
207+
}
208+
209+
return 0;
210+
}
211+
212+
static const struct of_device_id of_sky1_pcie_match[] = {
213+
{ .compatible = "cix,sky1-pcie-host", },
214+
{},
215+
};
216+
MODULE_DEVICE_TABLE(of, of_sky1_pcie_match);
217+
218+
static void sky1_pcie_remove(struct platform_device *pdev)
219+
{
220+
struct sky1_pcie *pcie = platform_get_drvdata(pdev);
221+
222+
pci_ecam_free(pcie->cfg);
223+
}
224+
225+
static struct platform_driver sky1_pcie_driver = {
226+
.probe = sky1_pcie_probe,
227+
.remove = sky1_pcie_remove,
228+
.driver = {
229+
.name = "sky1-pcie",
230+
.of_match_table = of_sky1_pcie_match,
231+
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
232+
},
233+
};
234+
module_platform_driver(sky1_pcie_driver);
235+
236+
MODULE_LICENSE("GPL");
237+
MODULE_DESCRIPTION("PCIe controller driver for CIX's sky1 SoCs");
238+
MODULE_AUTHOR("Hans Zhang <hans.zhang@cixtech.com>");

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