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Merge branch 'pci/controller/qcom'
- Export DWC MSI controller related APIs for use by upcoming DWC-based ECAM implementation (Mayank Rana) - Rename gen_pci_init() to pci_host_common_ecam_create() and export for use by controller drivers (Mayank Rana) - Add DT binding and driver support for SA8255p, which supports ECAM for Configuration Space access (Mayank Rana) - Update DT binding and driver to describe PHYs and per-Root Port resets in a Root Port stanza and deprecate describing them in the host bridge; this makes it possible to support multiple Root Ports in the future (Krishna Chaitanya Chundru) * pci/controller/qcom: PCI: qcom: Add support for parsing the new Root Port binding dt-bindings: PCI: qcom: Move PHY & reset GPIO to Root Port node PCI: qcom: Add support for Qualcomm SA8255p based PCIe Root Complex dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex PCI: host-generic: Rename and export gen_pci_init() for PCIe controller drivers PCI: dwc: Export DWC MSI controller related APIs
2 parents d5b0b60 + a2fbecd commit 81b3be6

9 files changed

Lines changed: 491 additions & 65 deletions

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‎Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml‎

Lines changed: 30 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -51,10 +51,18 @@ properties:
5151

5252
phys:
5353
maxItems: 1
54+
deprecated: true
55+
description:
56+
This property is deprecated, instead of referencing this property from
57+
the host bridge node, use the property from the PCIe root port node.
5458

5559
phy-names:
5660
items:
5761
- const: pciephy
62+
deprecated: true
63+
description:
64+
Phandle to the register map node. This property is deprecated, and not
65+
required to add in the root port also, as the root port has only one phy.
5866

5967
power-domains:
6068
maxItems: 1
@@ -71,12 +79,18 @@ properties:
7179
maxItems: 12
7280

7381
perst-gpios:
74-
description: GPIO controlled connection to PERST# signal
82+
description: GPIO controlled connection to PERST# signal. This property is
83+
deprecated, instead of referencing this property from the host bridge node,
84+
use the reset-gpios property from the root port node.
7585
maxItems: 1
86+
deprecated: true
7687

7788
wake-gpios:
78-
description: GPIO controlled connection to WAKE# signal
89+
description: GPIO controlled connection to WAKE# signal. This property is
90+
deprecated, instead of referencing this property from the host bridge node,
91+
use the property from the PCIe root port node.
7992
maxItems: 1
93+
deprecated: true
8094

8195
vddpe-3v3-supply:
8296
description: PCIe endpoint power supply
@@ -85,6 +99,20 @@ properties:
8599
opp-table:
86100
type: object
87101

102+
patternProperties:
103+
"^pcie@":
104+
type: object
105+
$ref: /schemas/pci/pci-pci-bridge.yaml#
106+
107+
properties:
108+
reg:
109+
maxItems: 1
110+
111+
phys:
112+
maxItems: 1
113+
114+
unevaluatedProperties: false
115+
88116
required:
89117
- reg
90118
- reg-names

‎Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml‎

Lines changed: 122 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,122 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8255p.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Qualcomm SA8255p based firmware managed and ECAM compliant PCIe Root Complex
8+
9+
maintainers:
10+
- Bjorn Andersson <andersson@kernel.org>
11+
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12+
13+
description:
14+
Qualcomm SA8255p SoC PCIe root complex controller is based on the Synopsys
15+
DesignWare PCIe IP which is managed by firmware, and configured in ECAM mode.
16+
17+
properties:
18+
compatible:
19+
const: qcom,pcie-sa8255p
20+
21+
reg:
22+
description:
23+
The base address and size of the ECAM area for accessing PCI
24+
Configuration Space, as accessed from the parent bus. The base
25+
address corresponds to the first bus in the "bus-range" property. If
26+
no "bus-range" is specified, this will be bus 0 (the default).
27+
maxItems: 1
28+
29+
ranges:
30+
description:
31+
As described in IEEE Std 1275-1994, but must provide at least a
32+
definition of non-prefetchable memory. One or both of prefetchable Memory
33+
may also be provided.
34+
minItems: 1
35+
maxItems: 2
36+
37+
interrupts:
38+
minItems: 8
39+
maxItems: 8
40+
41+
interrupt-names:
42+
items:
43+
- const: msi0
44+
- const: msi1
45+
- const: msi2
46+
- const: msi3
47+
- const: msi4
48+
- const: msi5
49+
- const: msi6
50+
- const: msi7
51+
52+
power-domains:
53+
maxItems: 1
54+
55+
dma-coherent: true
56+
iommu-map: true
57+
58+
required:
59+
- compatible
60+
- reg
61+
- ranges
62+
- power-domains
63+
- interrupts
64+
- interrupt-names
65+
66+
allOf:
67+
- $ref: /schemas/pci/pci-host-bridge.yaml#
68+
69+
unevaluatedProperties: false
70+
71+
examples:
72+
- |
73+
#include <dt-bindings/interrupt-controller/arm-gic.h>
74+
75+
soc {
76+
#address-cells = <2>;
77+
#size-cells = <2>;
78+
79+
pci@1c00000 {
80+
compatible = "qcom,pcie-sa8255p";
81+
reg = <0x4 0x00000000 0 0x10000000>;
82+
device_type = "pci";
83+
#address-cells = <3>;
84+
#size-cells = <2>;
85+
ranges = <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>,
86+
<0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x40000000>;
87+
bus-range = <0x00 0xff>;
88+
dma-coherent;
89+
linux,pci-domain = <0>;
90+
power-domains = <&scmi5_pd 0>;
91+
iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
92+
<0x100 &pcie_smmu 0x0001 0x1>;
93+
interrupt-parent = <&intc>;
94+
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
95+
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
96+
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
97+
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
98+
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
99+
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
100+
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
101+
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
102+
interrupt-names = "msi0", "msi1", "msi2", "msi3",
103+
"msi4", "msi5", "msi6", "msi7";
104+
105+
#interrupt-cells = <1>;
106+
interrupt-map-mask = <0 0 0 0x7>;
107+
interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
108+
<0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
109+
<0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
110+
<0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
111+
112+
pcie@0 {
113+
device_type = "pci";
114+
reg = <0x0 0x0 0x0 0x0 0x0>;
115+
bus-range = <0x01 0xff>;
116+
117+
#address-cells = <3>;
118+
#size-cells = <2>;
119+
ranges;
120+
};
121+
};
122+
};

‎Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml‎

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -165,9 +165,6 @@ examples:
165165
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
166166
<0x100 &apps_smmu 0x1c81 0x1>;
167167
168-
phys = <&pcie1_phy>;
169-
phy-names = "pciephy";
170-
171168
pinctrl-names = "default";
172169
pinctrl-0 = <&pcie1_clkreq_n>;
173170
@@ -176,7 +173,18 @@ examples:
176173
resets = <&gcc GCC_PCIE_1_BCR>;
177174
reset-names = "pci";
178175
179-
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
180176
vddpe-3v3-supply = <&pp3300_ssd>;
177+
pcie1_port0: pcie@0 {
178+
device_type = "pci";
179+
reg = <0x0 0x0 0x0 0x0 0x0>;
180+
bus-range = <0x01 0xff>;
181+
182+
#address-cells = <3>;
183+
#size-cells = <2>;
184+
ranges;
185+
phys = <&pcie1_phy>;
186+
187+
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
188+
};
181189
};
182190
};

‎drivers/pci/controller/dwc/Kconfig‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -297,6 +297,7 @@ config PCIE_QCOM
297297
select PCIE_DW_HOST
298298
select CRC8
299299
select PCIE_QCOM_COMMON
300+
select PCI_HOST_COMMON
300301
help
301302
Say Y here to enable PCIe controller support on Qualcomm SoCs. The
302303
PCIe controller uses the DesignWare core plus Qualcomm-specific

‎drivers/pci/controller/dwc/pcie-designware-host.c‎

Lines changed: 20 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -230,7 +230,7 @@ int dw_pcie_allocate_domains(struct dw_pcie_rp *pp)
230230
return 0;
231231
}
232232

233-
static void dw_pcie_free_msi(struct dw_pcie_rp *pp)
233+
void dw_pcie_free_msi(struct dw_pcie_rp *pp)
234234
{
235235
u32 ctrl;
236236

@@ -242,19 +242,34 @@ static void dw_pcie_free_msi(struct dw_pcie_rp *pp)
242242

243243
irq_domain_remove(pp->irq_domain);
244244
}
245+
EXPORT_SYMBOL_GPL(dw_pcie_free_msi);
245246

246-
static void dw_pcie_msi_init(struct dw_pcie_rp *pp)
247+
void dw_pcie_msi_init(struct dw_pcie_rp *pp)
247248
{
248249
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
249250
u64 msi_target = (u64)pp->msi_data;
251+
u32 ctrl, num_ctrls;
250252

251253
if (!pci_msi_enabled() || !pp->has_msi_ctrl)
252254
return;
253255

256+
num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
257+
258+
/* Initialize IRQ Status array */
259+
for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
260+
dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
261+
(ctrl * MSI_REG_CTRL_BLOCK_SIZE),
262+
pp->irq_mask[ctrl]);
263+
dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
264+
(ctrl * MSI_REG_CTRL_BLOCK_SIZE),
265+
~0);
266+
}
267+
254268
/* Program the msi_data */
255269
dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
256270
dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
257271
}
272+
EXPORT_SYMBOL_GPL(dw_pcie_msi_init);
258273

259274
static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp)
260275
{
@@ -296,7 +311,7 @@ static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp)
296311
return 0;
297312
}
298313

299-
static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
314+
int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
300315
{
301316
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
302317
struct device *dev = pci->dev;
@@ -370,6 +385,7 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
370385

371386
return 0;
372387
}
388+
EXPORT_SYMBOL_GPL(dw_pcie_msi_host_init);
373389

374390
static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp)
375391
{
@@ -888,7 +904,7 @@ static void dw_pcie_config_presets(struct dw_pcie_rp *pp)
888904
int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
889905
{
890906
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
891-
u32 val, ctrl, num_ctrls;
907+
u32 val;
892908
int ret;
893909

894910
/*
@@ -899,20 +915,6 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
899915

900916
dw_pcie_setup(pci);
901917

902-
if (pp->has_msi_ctrl) {
903-
num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
904-
905-
/* Initialize IRQ Status array */
906-
for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
907-
dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
908-
(ctrl * MSI_REG_CTRL_BLOCK_SIZE),
909-
pp->irq_mask[ctrl]);
910-
dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
911-
(ctrl * MSI_REG_CTRL_BLOCK_SIZE),
912-
~0);
913-
}
914-
}
915-
916918
dw_pcie_msi_init(pp);
917919

918920
/* Setup RC BARs */

‎drivers/pci/controller/dwc/pcie-designware.h‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -754,6 +754,9 @@ static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci)
754754
int dw_pcie_suspend_noirq(struct dw_pcie *pci);
755755
int dw_pcie_resume_noirq(struct dw_pcie *pci);
756756
irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp);
757+
void dw_pcie_msi_init(struct dw_pcie_rp *pp);
758+
int dw_pcie_msi_host_init(struct dw_pcie_rp *pp);
759+
void dw_pcie_free_msi(struct dw_pcie_rp *pp);
757760
int dw_pcie_setup_rc(struct dw_pcie_rp *pp);
758761
int dw_pcie_host_init(struct dw_pcie_rp *pp);
759762
void dw_pcie_host_deinit(struct dw_pcie_rp *pp);
@@ -776,6 +779,17 @@ static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
776779
return IRQ_NONE;
777780
}
778781

782+
static inline void dw_pcie_msi_init(struct dw_pcie_rp *pp)
783+
{ }
784+
785+
static inline int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
786+
{
787+
return -ENODEV;
788+
}
789+
790+
static inline void dw_pcie_free_msi(struct dw_pcie_rp *pp)
791+
{ }
792+
779793
static inline int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
780794
{
781795
return 0;

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