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Lucas De Marchi
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drm/xe/irq: Split irq mask per engine class
Each engine class has a different bitfield structure in the hw. We've been just using a common mask for all of them, but this means that we could inadvertently set a wrong bit in one class while enabling something in another. Split them to make it more future proof. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://lore.kernel.org/r/20251016-xe3p-v3-18-3dd173a3097a@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
1 parent 90a5cf0 commit 832bfaf

1 file changed

Lines changed: 47 additions & 26 deletions

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‎drivers/gpu/drm/xe/xe_irq.c‎

Lines changed: 47 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -139,25 +139,28 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
139139
{
140140
struct xe_device *xe = gt_to_xe(gt);
141141
struct xe_mmio *mmio = &gt->mmio;
142-
u32 irqs, dmask, smask;
143-
u32 gsc_mask = 0;
144-
u32 heci_mask = 0;
142+
u32 common_mask, val, gsc_mask = 0, heci_mask = 0,
143+
rcs_mask = 0, bcs_mask = 0, vcs_mask = 0, vecs_mask = 0,
144+
ccs_mask = 0;
145145

146146
if (xe_device_uses_memirq(xe))
147147
return;
148148

149149
if (xe_device_uc_enabled(xe)) {
150-
irqs = GT_RENDER_USER_INTERRUPT |
151-
GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
150+
common_mask = GT_RENDER_USER_INTERRUPT |
151+
GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
152152
} else {
153-
irqs = GT_RENDER_USER_INTERRUPT |
154-
GT_CS_MASTER_ERROR_INTERRUPT |
155-
GT_CONTEXT_SWITCH_INTERRUPT |
156-
GT_WAIT_SEMAPHORE_INTERRUPT;
153+
common_mask = GT_RENDER_USER_INTERRUPT |
154+
GT_CS_MASTER_ERROR_INTERRUPT |
155+
GT_CONTEXT_SWITCH_INTERRUPT |
156+
GT_WAIT_SEMAPHORE_INTERRUPT;
157157
}
158158

159-
dmask = irqs << 16 | irqs;
160-
smask = irqs << 16;
159+
rcs_mask |= common_mask;
160+
bcs_mask |= common_mask;
161+
vcs_mask |= common_mask;
162+
vecs_mask |= common_mask;
163+
ccs_mask |= common_mask;
161164

162165
if (xe_gt_is_main_type(gt)) {
163166
/*
@@ -169,44 +172,62 @@ void xe_irq_enable_hwe(struct xe_gt *gt)
169172
u32 bcs_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COPY);
170173

171174
/* Enable interrupts for each engine class */
172-
xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);
175+
xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE,
176+
REG_FIELD_PREP(ENGINE1_MASK, rcs_mask) |
177+
REG_FIELD_PREP(ENGINE0_MASK, bcs_mask));
173178
if (ccs_fuse_mask)
174-
xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);
179+
xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE,
180+
REG_FIELD_PREP(ENGINE1_MASK, ccs_mask));
175181

176182
/* Unmask interrupts for each engine instance */
177-
xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);
178-
xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);
183+
val = ~REG_FIELD_PREP(ENGINE1_MASK, rcs_mask);
184+
xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, val);
185+
val = ~REG_FIELD_PREP(ENGINE1_MASK, bcs_mask);
186+
xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, val);
187+
188+
val = ~(REG_FIELD_PREP(ENGINE1_MASK, bcs_mask) |
189+
REG_FIELD_PREP(ENGINE0_MASK, bcs_mask));
179190
if (bcs_fuse_mask & (BIT(1)|BIT(2)))
180-
xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
191+
xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, val);
181192
if (bcs_fuse_mask & (BIT(3)|BIT(4)))
182-
xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
193+
xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, val);
183194
if (bcs_fuse_mask & (BIT(5)|BIT(6)))
184-
xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
195+
xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, val);
185196
if (bcs_fuse_mask & (BIT(7)|BIT(8)))
186-
xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
197+
xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, val);
198+
199+
val = ~(REG_FIELD_PREP(ENGINE1_MASK, ccs_mask) |
200+
REG_FIELD_PREP(ENGINE0_MASK, ccs_mask));
187201
if (ccs_fuse_mask & (BIT(0)|BIT(1)))
188-
xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);
202+
xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, val);
189203
if (ccs_fuse_mask & (BIT(2)|BIT(3)))
190-
xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);
204+
xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, val);
191205
}
192206

193207
if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) {
194208
u32 other_fuse_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_OTHER);
195209

196210
/* Enable interrupts for each engine class */
197-
xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);
211+
xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE,
212+
REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
213+
REG_FIELD_PREP(ENGINE0_MASK, vecs_mask));
198214

199215
/* Unmask interrupts for each engine instance */
200-
xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~dmask);
201-
xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~dmask);
202-
xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~dmask);
216+
val = ~(REG_FIELD_PREP(ENGINE1_MASK, vcs_mask) |
217+
REG_FIELD_PREP(ENGINE0_MASK, vcs_mask));
218+
xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, val);
219+
xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, val);
220+
221+
val = ~(REG_FIELD_PREP(ENGINE1_MASK, vecs_mask) |
222+
REG_FIELD_PREP(ENGINE0_MASK, vecs_mask));
223+
xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, val);
203224

204225
/*
205226
* the heci2 interrupt is enabled via the same register as the
206227
* GSCCS interrupts, but it has its own mask register.
207228
*/
208229
if (other_fuse_mask) {
209-
gsc_mask = irqs | GSC_ER_COMPLETE;
230+
gsc_mask = common_mask | GSC_ER_COMPLETE;
210231
heci_mask = GSC_IRQ_INTF(1);
211232
} else if (xe->info.has_heci_gscfi) {
212233
gsc_mask = GSC_IRQ_INTF(1);

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