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chleroy
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mpe
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powerpc/boot: Remove all 40x platforms from boot
Remove 40x platforms from the boot directory. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20240628121201.130802-2-mpe@ellerman.id.au
1 parent 47d13a2 commit 839ff58

17 files changed

Lines changed: 1 addition & 2875 deletions

‎arch/powerpc/boot/4xx.c‎

Lines changed: 0 additions & 266 deletions
Original file line numberDiff line numberDiff line change
@@ -253,7 +253,6 @@ void ibm4xx_denali_fixup_memsize(void)
253253
dt_fixup_memory(0, memsize);
254254
}
255255

256-
#define SPRN_DBCR0_40X 0x3F2
257256
#define SPRN_DBCR0_44X 0x134
258257
#define DBCR0_RST_SYSTEM 0x30000000
259258

@@ -270,18 +269,6 @@ void ibm44x_dbcr_reset(void)
270269

271270
}
272271

273-
void ibm40x_dbcr_reset(void)
274-
{
275-
unsigned long tmp;
276-
277-
asm volatile (
278-
"mfspr %0,%1\n"
279-
"oris %0,%0,%2@h\n"
280-
"mtspr %1,%0"
281-
: "=&r"(tmp) : "i"(SPRN_DBCR0_40X), "i"(DBCR0_RST_SYSTEM)
282-
);
283-
}
284-
285272
#define EMAC_RESET 0x20000000
286273
void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
287274
{
@@ -544,256 +531,3 @@ void ibm440spe_fixup_clocks(unsigned int sys_clk,
544531
eplike_fixup_uart_clk(1, "/plb/opb/serial@f0000300", ser_clk, plb_clk);
545532
eplike_fixup_uart_clk(2, "/plb/opb/serial@f0000600", ser_clk, plb_clk);
546533
}
547-
548-
void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
549-
{
550-
u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
551-
u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
552-
u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);
553-
u32 psr = mfdcr(DCRN_405_CPC0_PSR);
554-
u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
555-
u32 fwdv, fwdvb, fbdv, cbdv, opdv, epdv, ppdv, udiv;
556-
557-
fwdv = (8 - ((pllmr & 0xe0000000) >> 29));
558-
fbdv = (pllmr & 0x1e000000) >> 25;
559-
if (fbdv == 0)
560-
fbdv = 16;
561-
cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
562-
opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
563-
ppdv = ((pllmr & 0x00006000) >> 13) + 1; /* PLB:PCI */
564-
epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */
565-
udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
566-
567-
/* check for 405GPr */
568-
if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) {
569-
fwdvb = 8 - (pllmr & 0x00000007);
570-
if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */
571-
if (psr & 0x00000020) /* New mode enable */
572-
m = fwdvb * 2 * ppdv;
573-
else
574-
m = fwdvb * cbdv * ppdv;
575-
else if (psr & 0x00000020) /* New mode enable */
576-
if (psr & 0x00000800) /* PerClk synch mode */
577-
m = fwdvb * 2 * epdv;
578-
else
579-
m = fbdv * fwdv;
580-
else if (epdv == fbdv)
581-
m = fbdv * cbdv * epdv;
582-
else
583-
m = fbdv * fwdvb * cbdv;
584-
585-
cpu = sys_clk * m / fwdv;
586-
plb = sys_clk * m / (fwdvb * cbdv);
587-
} else {
588-
m = fwdv * fbdv * cbdv;
589-
cpu = sys_clk * m / fwdv;
590-
plb = cpu / cbdv;
591-
}
592-
opb = plb / opdv;
593-
ebc = plb / epdv;
594-
595-
if (cpc0_cr0 & 0x80)
596-
/* uart0 uses the external clock */
597-
uart0 = ser_clk;
598-
else
599-
uart0 = cpu / udiv;
600-
601-
if (cpc0_cr0 & 0x40)
602-
/* uart1 uses the external clock */
603-
uart1 = ser_clk;
604-
else
605-
uart1 = cpu / udiv;
606-
607-
/* setup the timebase clock to tick at the cpu frequency */
608-
cpc0_cr1 = cpc0_cr1 & ~0x00800000;
609-
mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1);
610-
tb = cpu;
611-
612-
dt_fixup_cpu_clocks(cpu, tb, 0);
613-
dt_fixup_clock("/plb", plb);
614-
dt_fixup_clock("/plb/opb", opb);
615-
dt_fixup_clock("/plb/ebc", ebc);
616-
dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
617-
dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
618-
}
619-
620-
621-
void ibm405ep_fixup_clocks(unsigned int sys_clk)
622-
{
623-
u32 pllmr0 = mfdcr(DCRN_CPC0_PLLMR0);
624-
u32 pllmr1 = mfdcr(DCRN_CPC0_PLLMR1);
625-
u32 cpc0_ucr = mfdcr(DCRN_CPC0_UCR);
626-
u32 cpu, plb, opb, ebc, uart0, uart1;
627-
u32 fwdva, fwdvb, fbdv, cbdv, opdv, epdv;
628-
u32 pllmr0_ccdv, tb, m;
629-
630-
fwdva = 8 - ((pllmr1 & 0x00070000) >> 16);
631-
fwdvb = 8 - ((pllmr1 & 0x00007000) >> 12);
632-
fbdv = (pllmr1 & 0x00f00000) >> 20;
633-
if (fbdv == 0)
634-
fbdv = 16;
635-
636-
cbdv = ((pllmr0 & 0x00030000) >> 16) + 1; /* CPU:PLB */
637-
epdv = ((pllmr0 & 0x00000300) >> 8) + 2; /* PLB:EBC */
638-
opdv = ((pllmr0 & 0x00003000) >> 12) + 1; /* PLB:OPB */
639-
640-
m = fbdv * fwdvb;
641-
642-
pllmr0_ccdv = ((pllmr0 & 0x00300000) >> 20) + 1;
643-
if (pllmr1 & 0x80000000)
644-
cpu = sys_clk * m / (fwdva * pllmr0_ccdv);
645-
else
646-
cpu = sys_clk / pllmr0_ccdv;
647-
648-
plb = cpu / cbdv;
649-
opb = plb / opdv;
650-
ebc = plb / epdv;
651-
tb = cpu;
652-
uart0 = cpu / (cpc0_ucr & 0x0000007f);
653-
uart1 = cpu / ((cpc0_ucr & 0x00007f00) >> 8);
654-
655-
dt_fixup_cpu_clocks(cpu, tb, 0);
656-
dt_fixup_clock("/plb", plb);
657-
dt_fixup_clock("/plb/opb", opb);
658-
dt_fixup_clock("/plb/ebc", ebc);
659-
dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
660-
dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
661-
}
662-
663-
static u8 ibm405ex_fwdv_multi_bits[] = {
664-
/* values for: 1 - 16 */
665-
0x01, 0x02, 0x0e, 0x09, 0x04, 0x0b, 0x10, 0x0d, 0x0c, 0x05,
666-
0x06, 0x0f, 0x0a, 0x07, 0x08, 0x03
667-
};
668-
669-
u32 ibm405ex_get_fwdva(unsigned long cpr_fwdv)
670-
{
671-
u32 index;
672-
673-
for (index = 0; index < ARRAY_SIZE(ibm405ex_fwdv_multi_bits); index++)
674-
if (cpr_fwdv == (u32)ibm405ex_fwdv_multi_bits[index])
675-
return index + 1;
676-
677-
return 0;
678-
}
679-
680-
static u8 ibm405ex_fbdv_multi_bits[] = {
681-
/* values for: 1 - 100 */
682-
0x00, 0xff, 0x7e, 0xfd, 0x7a, 0xf5, 0x6a, 0xd5, 0x2a, 0xd4,
683-
0x29, 0xd3, 0x26, 0xcc, 0x19, 0xb3, 0x67, 0xce, 0x1d, 0xbb,
684-
0x77, 0xee, 0x5d, 0xba, 0x74, 0xe9, 0x52, 0xa5, 0x4b, 0x96,
685-
0x2c, 0xd8, 0x31, 0xe3, 0x46, 0x8d, 0x1b, 0xb7, 0x6f, 0xde,
686-
0x3d, 0xfb, 0x76, 0xed, 0x5a, 0xb5, 0x6b, 0xd6, 0x2d, 0xdb,
687-
0x36, 0xec, 0x59, 0xb2, 0x64, 0xc9, 0x12, 0xa4, 0x48, 0x91,
688-
0x23, 0xc7, 0x0e, 0x9c, 0x38, 0xf0, 0x61, 0xc2, 0x05, 0x8b,
689-
0x17, 0xaf, 0x5f, 0xbe, 0x7c, 0xf9, 0x72, 0xe5, 0x4a, 0x95,
690-
0x2b, 0xd7, 0x2e, 0xdc, 0x39, 0xf3, 0x66, 0xcd, 0x1a, 0xb4,
691-
0x68, 0xd1, 0x22, 0xc4, 0x09, 0x93, 0x27, 0xcf, 0x1e, 0xbc,
692-
/* values for: 101 - 200 */
693-
0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3,
694-
0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90,
695-
0x20, 0xc0, 0x01, 0x83, 0x07, 0x8f, 0x1f, 0xbf, 0x7f, 0xfe,
696-
0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6,
697-
0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd,
698-
0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1,
699-
0x63, 0xc6, 0x0d, 0x9b, 0x37, 0xef, 0x5e, 0xbd, 0x7b, 0xf6,
700-
0x6d, 0xda, 0x35, 0xeb, 0x56, 0xad, 0x5b, 0xb6, 0x6c, 0xd9,
701-
0x32, 0xe4, 0x49, 0x92, 0x24, 0xc8, 0x11, 0xa3, 0x47, 0x8e,
702-
0x1c, 0xb8, 0x70, 0xe1, 0x42, 0x85, 0x0b, 0x97, 0x2f, 0xdf,
703-
/* values for: 201 - 255 */
704-
0x3e, 0xfc, 0x79, 0xf2, 0x65, 0xca, 0x15, 0xab, 0x57, 0xae,
705-
0x5c, 0xb9, 0x73, 0xe6, 0x4d, 0x9a, 0x34, 0xe8, 0x51, 0xa2,
706-
0x44, 0x89, 0x13, 0xa7, 0x4f, 0x9e, 0x3c, 0xf8, 0x71, 0xe2,
707-
0x45, 0x8a, 0x14, 0xa8, 0x50, 0xa1, 0x43, 0x86, 0x0c, 0x98,
708-
0x30, 0xe0, 0x41, 0x82, 0x04, 0x88, 0x10, 0xa0, 0x40, 0x81,
709-
0x03, 0x87, 0x0f, 0x9f, 0x3f /* END */
710-
};
711-
712-
u32 ibm405ex_get_fbdv(unsigned long cpr_fbdv)
713-
{
714-
u32 index;
715-
716-
for (index = 0; index < ARRAY_SIZE(ibm405ex_fbdv_multi_bits); index++)
717-
if (cpr_fbdv == (u32)ibm405ex_fbdv_multi_bits[index])
718-
return index + 1;
719-
720-
return 0;
721-
}
722-
723-
void ibm405ex_fixup_clocks(unsigned int sys_clk, unsigned int uart_clk)
724-
{
725-
/* PLL config */
726-
u32 pllc = CPR0_READ(DCRN_CPR0_PLLC);
727-
u32 plld = CPR0_READ(DCRN_CPR0_PLLD);
728-
u32 cpud = CPR0_READ(DCRN_CPR0_PRIMAD);
729-
u32 plbd = CPR0_READ(DCRN_CPR0_PRIMBD);
730-
u32 opbd = CPR0_READ(DCRN_CPR0_OPBD);
731-
u32 perd = CPR0_READ(DCRN_CPR0_PERD);
732-
733-
/* Dividers */
734-
u32 fbdv = ibm405ex_get_fbdv(__fix_zero((plld >> 24) & 0xff, 1));
735-
736-
u32 fwdva = ibm405ex_get_fwdva(__fix_zero((plld >> 16) & 0x0f, 1));
737-
738-
u32 cpudv0 = __fix_zero((cpud >> 24) & 7, 8);
739-
740-
/* PLBDV0 is hardwared to 010. */
741-
u32 plbdv0 = 2;
742-
u32 plb2xdv0 = __fix_zero((plbd >> 16) & 7, 8);
743-
744-
u32 opbdv0 = __fix_zero((opbd >> 24) & 3, 4);
745-
746-
u32 perdv0 = __fix_zero((perd >> 24) & 3, 4);
747-
748-
/* Resulting clocks */
749-
u32 cpu, plb, opb, ebc, vco, tb, uart0, uart1;
750-
751-
/* PLL's VCO is the source for primary forward ? */
752-
if (pllc & 0x40000000) {
753-
u32 m;
754-
755-
/* Feedback path */
756-
switch ((pllc >> 24) & 7) {
757-
case 0:
758-
/* PLLOUTx */
759-
m = fbdv;
760-
break;
761-
case 1:
762-
/* CPU */
763-
m = fbdv * fwdva * cpudv0;
764-
break;
765-
case 5:
766-
/* PERClk */
767-
m = fbdv * fwdva * plb2xdv0 * plbdv0 * opbdv0 * perdv0;
768-
break;
769-
default:
770-
printf("WARNING ! Invalid PLL feedback source !\n");
771-
goto bypass;
772-
}
773-
774-
vco = (unsigned int)(sys_clk * m);
775-
} else {
776-
bypass:
777-
/* Bypass system PLL */
778-
vco = 0;
779-
}
780-
781-
/* CPU = VCO / ( FWDVA x CPUDV0) */
782-
cpu = vco / (fwdva * cpudv0);
783-
/* PLB = VCO / ( FWDVA x PLB2XDV0 x PLBDV0) */
784-
plb = vco / (fwdva * plb2xdv0 * plbdv0);
785-
/* OPB = PLB / OPBDV0 */
786-
opb = plb / opbdv0;
787-
/* EBC = OPB / PERDV0 */
788-
ebc = opb / perdv0;
789-
790-
tb = cpu;
791-
uart0 = uart1 = uart_clk;
792-
793-
dt_fixup_cpu_clocks(cpu, tb, 0);
794-
dt_fixup_clock("/plb", plb);
795-
dt_fixup_clock("/plb/opb", opb);
796-
dt_fixup_clock("/plb/opb/ebc", ebc);
797-
dt_fixup_clock("/plb/opb/serial@ef600200", uart0);
798-
dt_fixup_clock("/plb/opb/serial@ef600300", uart1);
799-
}

‎arch/powerpc/boot/4xx.h‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -12,13 +12,9 @@ void ibm4xx_sdram_fixup_memsize(void);
1212
void ibm440spe_fixup_memsize(void);
1313
void ibm4xx_denali_fixup_memsize(void);
1414
void ibm44x_dbcr_reset(void);
15-
void ibm40x_dbcr_reset(void);
1615
void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1);
1716
void ibm4xx_fixup_ebc_ranges(const char *ebc);
1817

19-
void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
20-
void ibm405ep_fixup_clocks(unsigned int sys_clk);
21-
void ibm405ex_fixup_clocks(unsigned int sys_clk, unsigned int uart_clk);
2218
void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
2319
void ibm440ep_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
2420
unsigned int tmr_clk);

‎arch/powerpc/boot/Makefile‎

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -54,10 +54,8 @@ endif
5454

5555
$(obj)/4xx.o: BOOTTARGETFLAGS += -mcpu=405
5656
$(obj)/ebony.o: BOOTTARGETFLAGS += -mcpu=440
57-
$(obj)/cuboot-hotfoot.o: BOOTTARGETFLAGS += -mcpu=405
5857
$(obj)/cuboot-taishan.o: BOOTTARGETFLAGS += -mcpu=440
5958
$(obj)/cuboot-katmai.o: BOOTTARGETFLAGS += -mcpu=440
60-
$(obj)/cuboot-acadia.o: BOOTTARGETFLAGS += -mcpu=405
6159
$(obj)/treeboot-iss4xx.o: BOOTTARGETFLAGS += -mcpu=405
6260
$(obj)/treeboot-currituck.o: BOOTTARGETFLAGS += -mcpu=405
6361
$(obj)/treeboot-akebono.o: BOOTTARGETFLAGS += -mcpu=405
@@ -146,17 +144,13 @@ src-wlib-$(CONFIG_PPC_POWERNV) += opal-calls.S opal.c
146144
ifndef CONFIG_PPC64_BOOT_WRAPPER
147145
src-wlib-y += crtsavres.S
148146
endif
149-
src-wlib-$(CONFIG_40x) += 4xx.c planetcore.c
150147
src-wlib-$(CONFIG_44x) += 4xx.c ebony.c bamboo.c
151148
src-wlib-$(CONFIG_PPC_8xx) += mpc8xx.c planetcore.c fsl-soc.c
152149
src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
153150
src-wlib-$(CONFIG_EMBEDDED6xx) += ugecon.c fsl-soc.c
154151
src-wlib-$(CONFIG_CPM) += cpm-serial.c
155152

156153
src-plat-y := of.c epapr.c
157-
src-plat-$(CONFIG_40x) += fixed-head.S cuboot-hotfoot.c \
158-
cuboot-acadia.c \
159-
cuboot-kilauea.c simpleboot.c
160154
src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
161155
cuboot-bamboo.c cuboot-sam440ep.c \
162156
cuboot-sequoia.c cuboot-rainier.c \
@@ -300,11 +294,6 @@ image-$(CONFIG_EPAPR_BOOT) += zImage.epapr
300294
# Boards with newish u-boot firmware can use the uImage target above
301295
#
302296

303-
# Board ports in arch/powerpc/platform/40x/Kconfig
304-
image-$(CONFIG_HOTFOOT) += cuImage.hotfoot
305-
image-$(CONFIG_ACADIA) += cuImage.acadia
306-
image-$(CONFIG_OBS600) += uImage.obs600
307-
308297
# Board ports in arch/powerpc/platform/44x/Kconfig
309298
image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
310299
image-$(CONFIG_BAMBOO) += treeImage.bamboo cuImage.bamboo

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