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shirazsaleemrleon
shirazsaleem
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rleon
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RDMA/irdma: Extend QP context programming for GEN3
Extend the QP context structure with support for new fields specific to GEN3 hardware capabilities. Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Tatyana Nikolova <tatyana.e.nikolova@intel.com> Link: https://patch.msgid.link/20250827152545.2056-10-tatyana.e.nikolova@intel.com Tested-by: Jacob Moroni <jmoroni@google.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>
1 parent d6ed4b6 commit 87f413b

5 files changed

Lines changed: 215 additions & 7 deletions

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‎drivers/infiniband/hw/irdma/ctrl.c‎

Lines changed: 181 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -637,13 +637,14 @@ static u8 irdma_sc_get_encoded_ird_size(u16 ird_size)
637637
}
638638

639639
/**
640-
* irdma_sc_qp_setctx_roce - set qp's context
640+
* irdma_sc_qp_setctx_roce_gen_2 - set qp's context
641641
* @qp: sc qp
642642
* @qp_ctx: context ptr
643643
* @info: ctx info
644644
*/
645-
void irdma_sc_qp_setctx_roce(struct irdma_sc_qp *qp, __le64 *qp_ctx,
646-
struct irdma_qp_host_ctx_info *info)
645+
static void irdma_sc_qp_setctx_roce_gen_2(struct irdma_sc_qp *qp,
646+
__le64 *qp_ctx,
647+
struct irdma_qp_host_ctx_info *info)
647648
{
648649
struct irdma_roce_offload_info *roce_info;
649650
struct irdma_udp_offload_info *udp;
@@ -761,6 +762,183 @@ void irdma_sc_qp_setctx_roce(struct irdma_sc_qp *qp, __le64 *qp_ctx,
761762
8, qp_ctx, IRDMA_QP_CTX_SIZE, false);
762763
}
763764

765+
/**
766+
* irdma_sc_get_encoded_ird_size_gen_3 - get encoded IRD size for GEN 3
767+
* @ird_size: IRD size
768+
* The ird from the connection is rounded to a supported HW setting and then encoded
769+
* for ird_size field of qp_ctx. Consumers are expected to provide valid ird size based
770+
* on hardware attributes. IRD size defaults to a value of 4 in case of invalid input.
771+
*/
772+
static u8 irdma_sc_get_encoded_ird_size_gen_3(u16 ird_size)
773+
{
774+
switch (ird_size ?
775+
roundup_pow_of_two(2 * ird_size) : 4) {
776+
case 4096:
777+
return IRDMA_IRD_HW_SIZE_4096_GEN3;
778+
case 2048:
779+
return IRDMA_IRD_HW_SIZE_2048_GEN3;
780+
case 1024:
781+
return IRDMA_IRD_HW_SIZE_1024_GEN3;
782+
case 512:
783+
return IRDMA_IRD_HW_SIZE_512_GEN3;
784+
case 256:
785+
return IRDMA_IRD_HW_SIZE_256_GEN3;
786+
case 128:
787+
return IRDMA_IRD_HW_SIZE_128_GEN3;
788+
case 64:
789+
return IRDMA_IRD_HW_SIZE_64_GEN3;
790+
case 32:
791+
return IRDMA_IRD_HW_SIZE_32_GEN3;
792+
case 16:
793+
return IRDMA_IRD_HW_SIZE_16_GEN3;
794+
case 8:
795+
return IRDMA_IRD_HW_SIZE_8_GEN3;
796+
case 4:
797+
default:
798+
break;
799+
}
800+
801+
return IRDMA_IRD_HW_SIZE_4_GEN3;
802+
}
803+
804+
/**
805+
* irdma_sc_qp_setctx_roce_gen_3 - set qp's context
806+
* @qp: sc qp
807+
* @qp_ctx: context ptr
808+
* @info: ctx info
809+
*/
810+
static void irdma_sc_qp_setctx_roce_gen_3(struct irdma_sc_qp *qp,
811+
__le64 *qp_ctx,
812+
struct irdma_qp_host_ctx_info *info)
813+
{
814+
struct irdma_roce_offload_info *roce_info = info->roce_info;
815+
struct irdma_udp_offload_info *udp = info->udp_info;
816+
u64 qw0, qw3, qw7 = 0, qw8 = 0;
817+
u8 push_mode_en;
818+
u32 push_idx;
819+
820+
qp->user_pri = info->user_pri;
821+
if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) {
822+
push_mode_en = 0;
823+
push_idx = 0;
824+
} else {
825+
push_mode_en = 1;
826+
push_idx = qp->push_idx;
827+
}
828+
829+
qw0 = FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) |
830+
FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) |
831+
FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) |
832+
FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) |
833+
FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) |
834+
FIELD_PREP(IRDMAQPC_PPIDX, push_idx) |
835+
FIELD_PREP(IRDMAQPC_PMENA, push_mode_en) |
836+
FIELD_PREP(IRDMAQPC_DC_TCP_EN, roce_info->dctcp_en) |
837+
FIELD_PREP(IRDMAQPC_ISQP1, roce_info->is_qp1) |
838+
FIELD_PREP(IRDMAQPC_ROCE_TVER, roce_info->roce_tver) |
839+
FIELD_PREP(IRDMAQPC_IPV4, udp->ipv4) |
840+
FIELD_PREP(IRDMAQPC_INSERTVLANTAG, udp->insert_vlan_tag);
841+
set_64bit_val(qp_ctx, 0, qw0);
842+
set_64bit_val(qp_ctx, 8, qp->sq_pa);
843+
set_64bit_val(qp_ctx, 16, qp->rq_pa);
844+
qw3 = FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) |
845+
FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size) |
846+
FIELD_PREP(IRDMAQPC_TTL, udp->ttl) |
847+
FIELD_PREP(IRDMAQPC_TOS, udp->tos) |
848+
FIELD_PREP(IRDMAQPC_SRCPORTNUM, udp->src_port) |
849+
FIELD_PREP(IRDMAQPC_DESTPORTNUM, udp->dst_port);
850+
set_64bit_val(qp_ctx, 24, qw3);
851+
set_64bit_val(qp_ctx, 32,
852+
FIELD_PREP(IRDMAQPC_DESTIPADDR2, udp->dest_ip_addr[2]) |
853+
FIELD_PREP(IRDMAQPC_DESTIPADDR3, udp->dest_ip_addr[3]));
854+
set_64bit_val(qp_ctx, 40,
855+
FIELD_PREP(IRDMAQPC_DESTIPADDR0, udp->dest_ip_addr[0]) |
856+
FIELD_PREP(IRDMAQPC_DESTIPADDR1, udp->dest_ip_addr[1]));
857+
set_64bit_val(qp_ctx, 48,
858+
FIELD_PREP(IRDMAQPC_SNDMSS, udp->snd_mss) |
859+
FIELD_PREP(IRDMAQPC_VLANTAG, udp->vlan_tag) |
860+
FIELD_PREP(IRDMAQPC_ARPIDX, udp->arp_idx));
861+
qw7 = FIELD_PREP(IRDMAQPC_PKEY, roce_info->p_key) |
862+
FIELD_PREP(IRDMAQPC_ACKCREDITS, roce_info->ack_credits) |
863+
FIELD_PREP(IRDMAQPC_FLOWLABEL, udp->flow_label);
864+
set_64bit_val(qp_ctx, 56, qw7);
865+
qw8 = FIELD_PREP(IRDMAQPC_QKEY, roce_info->qkey) |
866+
FIELD_PREP(IRDMAQPC_DESTQP, roce_info->dest_qp);
867+
set_64bit_val(qp_ctx, 64, qw8);
868+
set_64bit_val(qp_ctx, 80,
869+
FIELD_PREP(IRDMAQPC_PSNNXT, udp->psn_nxt) |
870+
FIELD_PREP(IRDMAQPC_LSN, udp->lsn));
871+
set_64bit_val(qp_ctx, 88,
872+
FIELD_PREP(IRDMAQPC_EPSN, udp->epsn));
873+
set_64bit_val(qp_ctx, 96,
874+
FIELD_PREP(IRDMAQPC_PSNMAX, udp->psn_max) |
875+
FIELD_PREP(IRDMAQPC_PSNUNA, udp->psn_una));
876+
set_64bit_val(qp_ctx, 112,
877+
FIELD_PREP(IRDMAQPC_CWNDROCE, udp->cwnd));
878+
set_64bit_val(qp_ctx, 128,
879+
FIELD_PREP(IRDMAQPC_MINRNR_TIMER, udp->min_rnr_timer) |
880+
FIELD_PREP(IRDMAQPC_RNRNAK_THRESH, udp->rnr_nak_thresh) |
881+
FIELD_PREP(IRDMAQPC_REXMIT_THRESH, udp->rexmit_thresh) |
882+
FIELD_PREP(IRDMAQPC_RNRNAK_TMR, udp->rnr_nak_tmr) |
883+
FIELD_PREP(IRDMAQPC_RTOMIN, roce_info->rtomin));
884+
set_64bit_val(qp_ctx, 136,
885+
FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) |
886+
FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num));
887+
set_64bit_val(qp_ctx, 152,
888+
FIELD_PREP(IRDMAQPC_MACADDRESS,
889+
ether_addr_to_u64(roce_info->mac_addr)) |
890+
FIELD_PREP(IRDMAQPC_LOCALACKTIMEOUT,
891+
roce_info->local_ack_timeout));
892+
set_64bit_val(qp_ctx, 160,
893+
FIELD_PREP(IRDMAQPC_ORDSIZE_GEN3, roce_info->ord_size) |
894+
FIELD_PREP(IRDMAQPC_IRDSIZE_GEN3,
895+
irdma_sc_get_encoded_ird_size_gen_3(roce_info->ird_size)) |
896+
FIELD_PREP(IRDMAQPC_WRRDRSPOK, roce_info->wr_rdresp_en) |
897+
FIELD_PREP(IRDMAQPC_RDOK, roce_info->rd_en) |
898+
FIELD_PREP(IRDMAQPC_USESTATSINSTANCE,
899+
info->stats_idx_valid) |
900+
FIELD_PREP(IRDMAQPC_BINDEN, roce_info->bind_en) |
901+
FIELD_PREP(IRDMAQPC_FASTREGEN, roce_info->fast_reg_en) |
902+
FIELD_PREP(IRDMAQPC_DCQCNENABLE, roce_info->dcqcn_en) |
903+
FIELD_PREP(IRDMAQPC_RCVNOICRC, roce_info->rcv_no_icrc) |
904+
FIELD_PREP(IRDMAQPC_FW_CC_ENABLE,
905+
roce_info->fw_cc_enable) |
906+
FIELD_PREP(IRDMAQPC_UDPRIVCQENABLE,
907+
roce_info->udprivcq_en) |
908+
FIELD_PREP(IRDMAQPC_PRIVEN, roce_info->priv_mode_en) |
909+
FIELD_PREP(IRDMAQPC_TIMELYENABLE, roce_info->timely_en));
910+
set_64bit_val(qp_ctx, 168,
911+
FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx));
912+
set_64bit_val(qp_ctx, 176,
913+
FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) |
914+
FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) |
915+
FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle));
916+
set_64bit_val(qp_ctx, 184,
917+
FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, udp->local_ipaddr[3]) |
918+
FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, udp->local_ipaddr[2]));
919+
set_64bit_val(qp_ctx, 192,
920+
FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, udp->local_ipaddr[1]) |
921+
FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, udp->local_ipaddr[0]));
922+
set_64bit_val(qp_ctx, 200,
923+
FIELD_PREP(IRDMAQPC_THIGH, roce_info->t_high) |
924+
FIELD_PREP(IRDMAQPC_TLOW, roce_info->t_low));
925+
set_64bit_val(qp_ctx, 208, roce_info->pd_id |
926+
FIELD_PREP(IRDMAQPC_STAT_INDEX_GEN3, info->stats_idx) |
927+
FIELD_PREP(IRDMAQPC_PKT_LIMIT, qp->pkt_limit));
928+
929+
print_hex_dump_debug("WQE: QP_HOST ROCE CTX WQE", DUMP_PREFIX_OFFSET,
930+
16, 8, qp_ctx, IRDMA_QP_CTX_SIZE, false);
931+
}
932+
933+
void irdma_sc_qp_setctx_roce(struct irdma_sc_qp *qp, __le64 *qp_ctx,
934+
struct irdma_qp_host_ctx_info *info)
935+
{
936+
if (qp->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2)
937+
irdma_sc_qp_setctx_roce_gen_2(qp, qp_ctx, info);
938+
else
939+
irdma_sc_qp_setctx_roce_gen_3(qp, qp_ctx, info);
940+
}
941+
764942
/* irdma_sc_alloc_local_mac_entry - allocate a mac entry
765943
* @cqp: struct for cqp hw
766944
* @scratch: u64 saved to be used during cqp completion

‎drivers/infiniband/hw/irdma/defs.h‎

Lines changed: 23 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,18 @@
1414
#define IRDMA_PE_DB_SIZE_4M 1
1515
#define IRDMA_PE_DB_SIZE_8M 2
1616

17+
#define IRDMA_IRD_HW_SIZE_4_GEN3 0
18+
#define IRDMA_IRD_HW_SIZE_8_GEN3 1
19+
#define IRDMA_IRD_HW_SIZE_16_GEN3 2
20+
#define IRDMA_IRD_HW_SIZE_32_GEN3 3
21+
#define IRDMA_IRD_HW_SIZE_64_GEN3 4
22+
#define IRDMA_IRD_HW_SIZE_128_GEN3 5
23+
#define IRDMA_IRD_HW_SIZE_256_GEN3 6
24+
#define IRDMA_IRD_HW_SIZE_512_GEN3 7
25+
#define IRDMA_IRD_HW_SIZE_1024_GEN3 8
26+
#define IRDMA_IRD_HW_SIZE_2048_GEN3 9
27+
#define IRDMA_IRD_HW_SIZE_4096_GEN3 10
28+
1729
#define IRDMA_IRD_HW_SIZE_4 0
1830
#define IRDMA_IRD_HW_SIZE_16 1
1931
#define IRDMA_IRD_HW_SIZE_64 2
@@ -836,7 +848,8 @@ enum irdma_cqp_op_type {
836848
#define IRDMAQPC_CWNDROCE GENMASK_ULL(55, 32)
837849
#define IRDMAQPC_SNDWL1 GENMASK_ULL(31, 0)
838850
#define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32)
839-
#define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(45, 32)
851+
#define IRDMAQPC_MINRNR_TIMER GENMASK_ULL(4, 0)
852+
#define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(46, 32)
840853
#define IRDMAQPC_RTOMIN GENMASK_ULL(63, 57)
841854
#define IRDMAQPC_MAXSNDWND GENMASK_ULL(31, 0)
842855
#define IRDMAQPC_REXMIT_THRESH GENMASK_ULL(53, 48)
@@ -849,8 +862,17 @@ enum irdma_cqp_op_type {
849862
#define IRDMAQPC_MACADDRESS GENMASK_ULL(63, 16)
850863
#define IRDMAQPC_ORDSIZE GENMASK_ULL(7, 0)
851864

865+
#define IRDMAQPC_LOCALACKTIMEOUT GENMASK_ULL(12, 8)
866+
#define IRDMAQPC_RNRNAK_TMR GENMASK_ULL(4, 0)
867+
#define IRDMAQPC_ORDSIZE_GEN3 GENMASK_ULL(10, 0)
868+
#define IRDMAQPC_REMOTE_ATOMIC_EN BIT_ULL(18)
869+
#define IRDMAQPC_STAT_INDEX_GEN3 GENMASK_ULL(47, 32)
870+
#define IRDMAQPC_PKT_LIMIT GENMASK_ULL(55, 48)
871+
852872
#define IRDMAQPC_IRDSIZE GENMASK_ULL(18, 16)
853873

874+
#define IRDMAQPC_IRDSIZE_GEN3 GENMASK_ULL(17, 14)
875+
854876
#define IRDMAQPC_UDPRIVCQENABLE BIT_ULL(19)
855877
#define IRDMAQPC_WRRDRSPOK BIT_ULL(20)
856878
#define IRDMAQPC_RDOK BIT_ULL(21)

‎drivers/infiniband/hw/irdma/type.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -574,6 +574,7 @@ struct irdma_sc_qp {
574574
bool flush_rq:1;
575575
bool sq_flush_code:1;
576576
bool rq_flush_code:1;
577+
u32 pkt_limit;
577578
enum irdma_flush_opcode flush_code;
578579
enum irdma_qp_event_type event_type;
579580
u8 term_flags;
@@ -915,6 +916,8 @@ struct irdma_udp_offload_info {
915916
u32 cwnd;
916917
u8 rexmit_thresh;
917918
u8 rnr_nak_thresh;
919+
u8 rnr_nak_tmr;
920+
u8 min_rnr_timer;
918921
};
919922

920923
struct irdma_roce_offload_info {
@@ -941,6 +944,7 @@ struct irdma_roce_offload_info {
941944
bool dctcp_en:1;
942945
bool fw_cc_enable:1;
943946
bool use_stats_inst:1;
947+
u8 local_ack_timeout;
944948
u16 t_high;
945949
u16 t_low;
946950
u8 last_byte_sent;

‎drivers/infiniband/hw/irdma/uda_d.h‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -78,8 +78,7 @@
7878
#define IRDMA_UDAQPC_IPID GENMASK_ULL(47, 32)
7979
#define IRDMA_UDAQPC_SNDMSS GENMASK_ULL(29, 16)
8080
#define IRDMA_UDAQPC_VLANTAG GENMASK_ULL(15, 0)
81-
82-
#define IRDMA_UDA_CQPSQ_MAV_PDINDEXHI GENMASK_ULL(21, 20)
81+
#define IRDMA_UDA_CQPSQ_MAV_PDINDEXHI GENMASK_ULL(27, 20)
8382
#define IRDMA_UDA_CQPSQ_MAV_PDINDEXLO GENMASK_ULL(63, 48)
8483
#define IRDMA_UDA_CQPSQ_MAV_SRCMACADDRINDEX GENMASK_ULL(29, 24)
8584
#define IRDMA_UDA_CQPSQ_MAV_ARPINDEX GENMASK_ULL(63, 48)
@@ -94,7 +93,7 @@
9493
#define IRDMA_UDA_CQPSQ_MAV_OPCODE GENMASK_ULL(37, 32)
9594
#define IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK BIT_ULL(62)
9695
#define IRDMA_UDA_CQPSQ_MAV_IPV4VALID BIT_ULL(59)
97-
#define IRDMA_UDA_CQPSQ_MAV_AVIDX GENMASK_ULL(16, 0)
96+
#define IRDMA_UDA_CQPSQ_MAV_AVIDX GENMASK_ULL(23, 0)
9897
#define IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG BIT_ULL(60)
9998
#define IRDMA_UDA_MGCTX_VFFLAG BIT_ULL(29)
10099
#define IRDMA_UDA_MGCTX_DESTPORT GENMASK_ULL(47, 32)

‎drivers/infiniband/hw/irdma/verbs.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1162,6 +1162,7 @@ static int irdma_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
11621162
attr->pkey_index = iwqp->roce_info.p_key;
11631163
attr->retry_cnt = iwqp->udp_info.rexmit_thresh;
11641164
attr->rnr_retry = iwqp->udp_info.rnr_nak_thresh;
1165+
attr->min_rnr_timer = iwqp->udp_info.min_rnr_timer;
11651166
attr->max_rd_atomic = iwqp->roce_info.ord_size;
11661167
attr->max_dest_rd_atomic = iwqp->roce_info.ird_size;
11671168
}
@@ -1294,6 +1295,10 @@ int irdma_modify_qp_roce(struct ib_qp *ibqp, struct ib_qp_attr *attr,
12941295
if (attr_mask & IB_QP_RNR_RETRY)
12951296
udp_info->rnr_nak_thresh = attr->rnr_retry;
12961297

1298+
if (attr_mask & IB_QP_MIN_RNR_TIMER &&
1299+
dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3)
1300+
udp_info->min_rnr_timer = attr->min_rnr_timer;
1301+
12971302
if (attr_mask & IB_QP_RETRY_CNT)
12981303
udp_info->rexmit_thresh = attr->retry_cnt;
12991304

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