@@ -1489,6 +1489,10 @@ static void domain_flush_pages(struct protection_domain *domain,
14891489{
14901490 if (likely (!amd_iommu_np_cache )) {
14911491 __domain_flush_pages (domain , address , size );
1492+
1493+ /* Wait until IOMMU TLB and all device IOTLB flushes are complete */
1494+ amd_iommu_domain_flush_complete (domain );
1495+
14921496 return ;
14931497 }
14941498
@@ -1525,6 +1529,9 @@ static void domain_flush_pages(struct protection_domain *domain,
15251529 address += flush_size ;
15261530 size -= flush_size ;
15271531 }
1532+
1533+ /* Wait until IOMMU TLB and all device IOTLB flushes are complete */
1534+ amd_iommu_domain_flush_complete (domain );
15281535}
15291536
15301537/* Flush the whole IO/TLB for a given protection domain - including PDE */
@@ -1558,7 +1565,6 @@ static void domain_flush_np_cache(struct protection_domain *domain,
15581565
15591566 spin_lock_irqsave (& domain -> lock , flags );
15601567 domain_flush_pages (domain , iova , size );
1561- amd_iommu_domain_flush_complete (domain );
15621568 spin_unlock_irqrestore (& domain -> lock , flags );
15631569 }
15641570}
@@ -1836,12 +1842,9 @@ static void do_detach(struct iommu_dev_data *dev_data)
18361842 /* Flush the DTE entry */
18371843 device_flush_dte (dev_data );
18381844
1839- /* Flush IOTLB */
1845+ /* Flush IOTLB and wait for the flushes to finish */
18401846 amd_iommu_domain_flush_tlb_pde (domain );
18411847
1842- /* Wait for the flushes to finish */
1843- amd_iommu_domain_flush_complete (domain );
1844-
18451848 /* decrease reference counters - needs to happen after the flushes */
18461849 domain -> dev_iommu [iommu -> index ] -= 1 ;
18471850 domain -> dev_cnt -= 1 ;
@@ -2018,7 +2021,6 @@ void amd_iommu_domain_update(struct protection_domain *domain)
20182021
20192022 /* Flush domain TLB(s) and wait for completion */
20202023 amd_iommu_domain_flush_tlb_pde (domain );
2021- amd_iommu_domain_flush_complete (domain );
20222024}
20232025
20242026/*****************************************************************************
@@ -2451,10 +2453,9 @@ static int amd_iommu_set_dirty_tracking(struct iommu_domain *domain,
24512453 }
24522454
24532455 /* Flush IOTLB to mark IOPTE dirty on the next translation(s) */
2454- if (domain_flush ) {
2456+ if (domain_flush )
24552457 amd_iommu_domain_flush_tlb_pde (pdomain );
2456- amd_iommu_domain_flush_complete (pdomain );
2457- }
2458+
24582459 pdomain -> dirty_tracking = enable ;
24592460 spin_unlock_irqrestore (& pdomain -> lock , flags );
24602461
@@ -2558,7 +2559,6 @@ static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
25582559
25592560 spin_lock_irqsave (& dom -> lock , flags );
25602561 amd_iommu_domain_flush_tlb_pde (dom );
2561- amd_iommu_domain_flush_complete (dom );
25622562 spin_unlock_irqrestore (& dom -> lock , flags );
25632563}
25642564
@@ -2570,7 +2570,6 @@ static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
25702570
25712571 spin_lock_irqsave (& dom -> lock , flags );
25722572 domain_flush_pages (dom , gather -> start , gather -> end - gather -> start + 1 );
2573- amd_iommu_domain_flush_complete (dom );
25742573 spin_unlock_irqrestore (& dom -> lock , flags );
25752574}
25762575
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