Skip to content

Commit 8df0cdc

Browse files
author
Alexandre Ghiti
committed
Merge patch series "RISC-V: clarify what some RISCV_ISA* config options do & redo Zbb toolchain dependency"
Conor Dooley <conor@kernel.org> says: Since one depends on the other, albeit trivially, here's a v4 of the Zbb toolchain dep removal alongside the rewording of Kconfig options I'd sent out before the merge window. I think I like this implementation better than v1, but I couldn't think of a good name for a "public" version of __ALTERNATIVE(), so I used it here directly. Unfortunately "ALTERNATIVE_2_CFG" already exists and I couldn't think of a good way to name an alternative macro that allows for several config options that didn't make the distinction sufficiently clear.. Yell if you have better suggestions than I did. I am a wee bit "worried" that this makes the Kconfig option confusing as it isn't immediately obvious if someone is or is not going to get the toolchain based optimisations. Cheers, Conor. * patches from https://lore.kernel.org/r/20241024-aspire-rectify-9982da6943e5@spud: RISC-V: separate Zbb optimisations requiring and not requiring toolchain support RISC-V: clarify what some RISCV_ISA* config options do Link: https://lore.kernel.org/r/20241024-aspire-rectify-9982da6943e5@spud Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
2 parents 4701f33 + 9343aab commit 8df0cdc

8 files changed

Lines changed: 38 additions & 49 deletions

File tree

‎arch/riscv/Kconfig‎

Lines changed: 20 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -566,7 +566,8 @@ config RISCV_ISA_C
566566
help
567567
Adds "C" to the ISA subsets that the toolchain is allowed to emit
568568
when building Linux, which results in compressed instructions in the
569-
Linux binary.
569+
Linux binary. This option produces a kernel that will not run on
570+
systems that do not support compressed instructions.
570571

571572
If you don't know what to do here, say Y.
572573

@@ -587,8 +588,8 @@ config RISCV_ISA_SVNAPOT
587588
depends on RISCV_ALTERNATIVE
588589
default y
589590
help
590-
Allow kernel to detect the Svnapot ISA-extension dynamically at boot
591-
time and enable its usage.
591+
Enable support for the Svnapot ISA-extension when it is detected
592+
at boot.
592593

593594
The Svnapot extension is used to mark contiguous PTEs as a range
594595
of contiguous virtual-to-physical translations for a naturally
@@ -606,9 +607,8 @@ config RISCV_ISA_SVPBMT
606607
depends on RISCV_ALTERNATIVE
607608
default y
608609
help
609-
Adds support to dynamically detect the presence of the Svpbmt
610-
ISA-extension (Supervisor-mode: page-based memory types) and
611-
enable its usage.
610+
Add support for the Svpbmt ISA-extension (Supervisor-mode:
611+
page-based memory types) in the kernel when it is detected at boot.
612612

613613
The memory type for a page contains a combination of attributes
614614
that indicate the cacheability, idempotency, and ordering
@@ -627,14 +627,15 @@ config TOOLCHAIN_HAS_V
627627
depends on AS_HAS_OPTION_ARCH
628628

629629
config RISCV_ISA_V
630-
bool "VECTOR extension support"
630+
bool "Vector extension support"
631631
depends on TOOLCHAIN_HAS_V
632632
depends on FPU
633633
select DYNAMIC_SIGFRAME
634634
default y
635635
help
636-
Say N here if you want to disable all vector related procedure
637-
in the kernel.
636+
Add support for the Vector extension when it is detected at boot.
637+
When this option is disabled, neither the kernel nor userspace may
638+
use vector procedures.
638639

639640
If you don't know what to do here, say Y.
640641

@@ -747,12 +748,12 @@ config RISCV_ISA_ZBA
747748

748749
config RISCV_ISA_ZBB
749750
bool "Zbb extension support for bit manipulation instructions"
750-
depends on TOOLCHAIN_HAS_ZBB
751751
depends on RISCV_ALTERNATIVE
752752
default y
753753
help
754-
Adds support to dynamically detect the presence of the ZBB
755-
extension (basic bit manipulation) and enable its usage.
754+
Add support for enabling optimisations in the kernel when the
755+
Zbb extension is detected at boot. Some optimisations may
756+
additionally depend on toolchain support for Zbb.
756757

757758
The Zbb extension provides instructions to accelerate a number
758759
of bit-specific operations (count bit population, sign extending,
@@ -791,9 +792,9 @@ config RISCV_ISA_ZICBOM
791792
select RISCV_DMA_NONCOHERENT
792793
select DMA_DIRECT_REMAP
793794
help
794-
Adds support to dynamically detect the presence of the ZICBOM
795-
extension (Cache Block Management Operations) and enable its
796-
usage.
795+
Add support for the Zicbom extension (Cache Block Management
796+
Operations) and enable its use in the kernel when it is detected
797+
at boot.
797798

798799
The Zicbom extension can be used to handle for example
799800
non-coherent DMA support on devices that need it.
@@ -806,7 +807,7 @@ config RISCV_ISA_ZICBOZ
806807
default y
807808
help
808809
Enable the use of the Zicboz extension (cbo.zero instruction)
809-
when available.
810+
in the kernel when it is detected at boot.
810811

811812
The Zicboz extension is used for faster zeroing of memory.
812813

@@ -844,8 +845,9 @@ config FPU
844845
bool "FPU support"
845846
default y
846847
help
847-
Say N here if you want to disable all floating-point related procedure
848-
in the kernel.
848+
Add support for floating point operations when an FPU is detected at
849+
boot. When this option is disabled, neither the kernel nor userspace
850+
may use the floating point unit.
849851

850852
If you don't know what to do here, say Y.
851853

‎arch/riscv/include/asm/arch_hweight.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919

2020
static __always_inline unsigned int __arch_hweight32(unsigned int w)
2121
{
22-
#ifdef CONFIG_RISCV_ISA_ZBB
22+
#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)
2323
asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
2424
RISCV_ISA_EXT_ZBB, 1)
2525
: : : : legacy);
@@ -50,7 +50,7 @@ static inline unsigned int __arch_hweight8(unsigned int w)
5050
#if BITS_PER_LONG == 64
5151
static __always_inline unsigned long __arch_hweight64(__u64 w)
5252
{
53-
# ifdef CONFIG_RISCV_ISA_ZBB
53+
#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)
5454
asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
5555
RISCV_ISA_EXT_ZBB, 1)
5656
: : : : legacy);
@@ -64,7 +64,7 @@ static __always_inline unsigned long __arch_hweight64(__u64 w)
6464
return w;
6565

6666
legacy:
67-
# endif
67+
#endif
6868
return __sw_hweight64(w);
6969
}
7070
#else /* BITS_PER_LONG == 64 */

‎arch/riscv/include/asm/bitops.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515
#include <asm/barrier.h>
1616
#include <asm/bitsperlong.h>
1717

18-
#if !defined(CONFIG_RISCV_ISA_ZBB) || defined(NO_ALTERNATIVE)
18+
#if !(defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)) || defined(NO_ALTERNATIVE)
1919
#include <asm-generic/bitops/__ffs.h>
2020
#include <asm-generic/bitops/__fls.h>
2121
#include <asm-generic/bitops/ffs.h>
@@ -175,7 +175,7 @@ static __always_inline int variable_fls(unsigned int x)
175175
variable_fls(x_); \
176176
})
177177

178-
#endif /* !defined(CONFIG_RISCV_ISA_ZBB) || defined(NO_ALTERNATIVE) */
178+
#endif /* !(defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)) || defined(NO_ALTERNATIVE) */
179179

180180
#include <asm-generic/bitops/ffz.h>
181181
#include <asm-generic/bitops/fls64.h>

‎arch/riscv/include/asm/checksum.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -49,8 +49,7 @@ static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
4949
* ZBB only saves three instructions on 32-bit and five on 64-bit so not
5050
* worth checking if supported without Alternatives.
5151
*/
52-
if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&
53-
IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
52+
if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {
5453
unsigned long fold_temp;
5554

5655
asm goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0,

‎arch/riscv/lib/csum.c‎

Lines changed: 3 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -40,12 +40,7 @@ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
4040
uproto = (__force unsigned int)htonl(proto);
4141
sum += uproto;
4242

43-
/*
44-
* Zbb support saves 4 instructions, so not worth checking without
45-
* alternatives if supported
46-
*/
47-
if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&
48-
IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
43+
if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {
4944
unsigned long fold_temp;
5045

5146
/*
@@ -157,12 +152,7 @@ do_csum_with_alignment(const unsigned char *buff, int len)
157152
csum = do_csum_common(ptr, end, data);
158153

159154
#ifdef CC_HAS_ASM_GOTO_TIED_OUTPUT
160-
/*
161-
* Zbb support saves 6 instructions, so not worth checking without
162-
* alternatives if supported
163-
*/
164-
if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&
165-
IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
155+
if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {
166156
unsigned long fold_temp;
167157

168158
/*
@@ -244,12 +234,7 @@ do_csum_no_alignment(const unsigned char *buff, int len)
244234
end = (const unsigned long *)(buff + len);
245235
csum = do_csum_common(ptr, end, data);
246236

247-
/*
248-
* Zbb support saves 6 instructions, so not worth checking without
249-
* alternatives if supported
250-
*/
251-
if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&
252-
IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
237+
if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {
253238
unsigned long fold_temp;
254239

255240
/*

‎arch/riscv/lib/strcmp.S‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,8 @@
88
/* int strcmp(const char *cs, const char *ct) */
99
SYM_FUNC_START(strcmp)
1010

11-
ALTERNATIVE("nop", "j strcmp_zbb", 0, RISCV_ISA_EXT_ZBB, CONFIG_RISCV_ISA_ZBB)
11+
__ALTERNATIVE_CFG("nop", "j strcmp_zbb", 0, RISCV_ISA_EXT_ZBB,
12+
IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB))
1213

1314
/*
1415
* Returns
@@ -43,7 +44,7 @@ SYM_FUNC_START(strcmp)
4344
* The code was published as part of the bitmanip manual
4445
* in Appendix A.
4546
*/
46-
#ifdef CONFIG_RISCV_ISA_ZBB
47+
#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)
4748
strcmp_zbb:
4849

4950
.option push

‎arch/riscv/lib/strlen.S‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,8 @@
88
/* int strlen(const char *s) */
99
SYM_FUNC_START(strlen)
1010

11-
ALTERNATIVE("nop", "j strlen_zbb", 0, RISCV_ISA_EXT_ZBB, CONFIG_RISCV_ISA_ZBB)
11+
__ALTERNATIVE_CFG("nop", "j strlen_zbb", 0, RISCV_ISA_EXT_ZBB,
12+
IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB))
1213

1314
/*
1415
* Returns
@@ -33,7 +34,7 @@ SYM_FUNC_START(strlen)
3334
/*
3435
* Variant of strlen using the ZBB extension if available
3536
*/
36-
#ifdef CONFIG_RISCV_ISA_ZBB
37+
#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)
3738
strlen_zbb:
3839

3940
#ifdef CONFIG_CPU_BIG_ENDIAN

‎arch/riscv/lib/strncmp.S‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,8 @@
88
/* int strncmp(const char *cs, const char *ct, size_t count) */
99
SYM_FUNC_START(strncmp)
1010

11-
ALTERNATIVE("nop", "j strncmp_zbb", 0, RISCV_ISA_EXT_ZBB, CONFIG_RISCV_ISA_ZBB)
11+
__ALTERNATIVE_CFG("nop", "j strncmp_zbb", 0, RISCV_ISA_EXT_ZBB,
12+
IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB))
1213

1314
/*
1415
* Returns
@@ -46,7 +47,7 @@ SYM_FUNC_START(strncmp)
4647
/*
4748
* Variant of strncmp using the ZBB extension if available
4849
*/
49-
#ifdef CONFIG_RISCV_ISA_ZBB
50+
#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)
5051
strncmp_zbb:
5152

5253
.option push

0 commit comments

Comments
 (0)