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Merge patch series "Add SpacemiT K1 USB3.0 host controller support"
Ze Huang <huang.ze@linux.dev> says: The USB 3.0 controller found in the SpacemiT K1 SoC[1] supports both USB3.0 Host and USB2.0 Dual-Role Device (DRD). This controller is compatible with DesignWare Core USB 3 (DWC3) driver. However, constraints in the `snps,dwc3` bindings limit the ability to describe hardware-specific features in a clean and maintainable way. While `dwc3-of-simple` still serves as a glue layer for many platforms, it requires a split device tree node structure, which is less desirable in newer platforms. To promote a transition toward a flattened `dwc` node structure, this series introduces `dwc3-generic-plat`, building upon prior efforts that exposed the DWC3 core driver [2]. The device tree support for SpacemiT K1 will be submitted separately when the associated PHY driver is ready. Link: https://developer.spacemit.com/documentation?token=AjHDwrW78igAAEkiHracBI9HnTb [1] Link: https://lore.kernel.org/all/20250414-dwc3-refactor-v7-3-f015b358722d@oss.qualcomm.com [2] Link: https://lore.kernel.org/r/20250913-dwc3_generic-v8-0-b50f81f05f95@linux.dev Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2 parents a4d43c1 + e0b6dc0 commit 9042221

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/spacemit,k1-dwc3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SpacemiT K1 SuperSpeed DWC3 USB SoC Controller
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maintainers:
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- Ze Huang <huang.ze@linux.dev>
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description: |
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The SpacemiT K1 embeds a DWC3 USB IP Core which supports Host functions
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for USB 3.0 and DRD for USB 2.0.
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Key features:
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- USB3.0 SuperSpeed and USB2.0 High/Full/Low-Speed support
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- Supports low-power modes (USB2.0 suspend, USB3.0 U1/U2/U3)
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- Internal DMA controller and flexible endpoint FIFO sizing
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Communication Interface:
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- Use of PIPE3 (125MHz) interface for USB3.0 PHY
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- Use of UTMI+ (30/60MHz) interface for USB2.0 PHY
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allOf:
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- $ref: snps,dwc3-common.yaml#
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properties:
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compatible:
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const: spacemit,k1-dwc3
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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const: usbdrd30
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interrupts:
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maxItems: 1
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phys:
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items:
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- description: phandle to USB2/HS PHY
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- description: phandle to USB3/SS PHY
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phy-names:
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items:
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- const: usb2-phy
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- const: usb3-phy
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resets:
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items:
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- description: USB3.0 AHB reset
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- description: USB3.0 VCC reset
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- description: USB3.0 PHY reset
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reset-names:
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items:
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- const: ahb
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- const: vcc
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- const: phy
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reset-delay:
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 2
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description: delay after reset sequence [us]
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vbus-supply:
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description: A phandle to the regulator supplying the VBUS voltage.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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- phys
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- phy-names
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- resets
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- reset-names
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unevaluatedProperties: false
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examples:
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- |
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usb@c0a00000 {
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compatible = "spacemit,k1-dwc3";
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reg = <0xc0a00000 0x10000>;
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clocks = <&syscon_apmu 16>;
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clock-names = "usbdrd30";
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interrupts = <125>;
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phys = <&usb2phy>, <&usb3phy>;
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phy-names = "usb2-phy", "usb3-phy";
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resets = <&syscon_apmu 8>,
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<&syscon_apmu 9>,
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<&syscon_apmu 10>;
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reset-names = "ahb", "vcc", "phy";
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reset-delay = <2>;
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vbus-supply = <&usb3_vbus>;
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#address-cells = <1>;
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#size-cells = <0>;
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hub_2_0: hub@1 {
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compatible = "usb2109,2817";
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reg = <1>;
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vdd-supply = <&usb3_vhub>;
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peer-hub = <&hub_3_0>;
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reset-gpios = <&gpio 3 28 1>;
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};
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hub_3_0: hub@2 {
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compatible = "usb2109,817";
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reg = <2>;
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vdd-supply = <&usb3_vhub>;
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peer-hub = <&hub_2_0>;
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reset-gpios = <&gpio 3 28 1>;
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};
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};

drivers/usb/dwc3/Kconfig

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or dual-role mode.
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Say 'Y' or 'M' if you have such device.
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config USB_DWC3_GENERIC_PLAT
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tristate "DWC3 Generic Platform Driver"
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depends on OF && COMMON_CLK
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default USB_DWC3
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help
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Support USB3 functionality in simple SoC integrations.
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Currently supports SpacemiT DWC USB3. Platforms using
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dwc3-of-simple can easily switch to dwc3-generic by flattening
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the dwc3 child node in the device tree.
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Say 'Y' or 'M' here if your platform integrates DWC3 in a similar way.
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endif

drivers/usb/dwc3/Makefile

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obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o
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obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o
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obj-$(CONFIG_USB_DWC3_RTK) += dwc3-rtk.o
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obj-$(CONFIG_USB_DWC3_GENERIC_PLAT) += dwc3-generic-plat.o
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* dwc3-generic-plat.c - DesignWare USB3 generic platform driver
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*
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* Copyright (C) 2025 Ze Huang <huang.ze@linux.dev>
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*
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* Inspired by dwc3-qcom.c and dwc3-of-simple.c
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*/
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include "glue.h"
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struct dwc3_generic {
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struct device *dev;
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struct dwc3 dwc;
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struct clk_bulk_data *clks;
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int num_clocks;
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struct reset_control *resets;
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};
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#define to_dwc3_generic(d) container_of((d), struct dwc3_generic, dwc)
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static void dwc3_generic_reset_control_assert(void *data)
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{
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reset_control_assert(data);
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}
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static int dwc3_generic_probe(struct platform_device *pdev)
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{
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struct dwc3_probe_data probe_data = {};
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struct device *dev = &pdev->dev;
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struct dwc3_generic *dwc3g;
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struct resource *res;
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int ret;
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dwc3g = devm_kzalloc(dev, sizeof(*dwc3g), GFP_KERNEL);
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if (!dwc3g)
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return -ENOMEM;
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dwc3g->dev = dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "missing memory resource\n");
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return -ENODEV;
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}
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dwc3g->resets = devm_reset_control_array_get_optional_exclusive(dev);
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if (IS_ERR(dwc3g->resets))
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return dev_err_probe(dev, PTR_ERR(dwc3g->resets), "failed to get resets\n");
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ret = reset_control_assert(dwc3g->resets);
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if (ret)
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return dev_err_probe(dev, ret, "failed to assert resets\n");
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/* Not strict timing, just for safety */
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udelay(2);
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ret = reset_control_deassert(dwc3g->resets);
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if (ret)
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return dev_err_probe(dev, ret, "failed to deassert resets\n");
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ret = devm_add_action_or_reset(dev, dwc3_generic_reset_control_assert, dwc3g->resets);
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if (ret)
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return ret;
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ret = devm_clk_bulk_get_all_enabled(dwc3g->dev, &dwc3g->clks);
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if (ret < 0)
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return dev_err_probe(dev, ret, "failed to get clocks\n");
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dwc3g->num_clocks = ret;
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dwc3g->dwc.dev = dev;
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probe_data.dwc = &dwc3g->dwc;
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probe_data.res = res;
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probe_data.ignore_clocks_and_resets = true;
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ret = dwc3_core_probe(&probe_data);
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if (ret)
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return dev_err_probe(dev, ret, "failed to register DWC3 Core\n");
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return 0;
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}
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static void dwc3_generic_remove(struct platform_device *pdev)
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{
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struct dwc3 *dwc = platform_get_drvdata(pdev);
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struct dwc3_generic *dwc3g = to_dwc3_generic(dwc);
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dwc3_core_remove(dwc);
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clk_bulk_disable_unprepare(dwc3g->num_clocks, dwc3g->clks);
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}
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static int dwc3_generic_suspend(struct device *dev)
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{
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struct dwc3 *dwc = dev_get_drvdata(dev);
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struct dwc3_generic *dwc3g = to_dwc3_generic(dwc);
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int ret;
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ret = dwc3_pm_suspend(dwc);
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if (ret)
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return ret;
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clk_bulk_disable_unprepare(dwc3g->num_clocks, dwc3g->clks);
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return 0;
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}
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static int dwc3_generic_resume(struct device *dev)
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{
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struct dwc3 *dwc = dev_get_drvdata(dev);
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struct dwc3_generic *dwc3g = to_dwc3_generic(dwc);
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int ret;
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ret = clk_bulk_prepare_enable(dwc3g->num_clocks, dwc3g->clks);
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if (ret)
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return ret;
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ret = dwc3_pm_resume(dwc);
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if (ret)
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return ret;
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return 0;
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}
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static int dwc3_generic_runtime_suspend(struct device *dev)
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{
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return dwc3_runtime_suspend(dev_get_drvdata(dev));
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}
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static int dwc3_generic_runtime_resume(struct device *dev)
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{
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return dwc3_runtime_resume(dev_get_drvdata(dev));
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}
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static int dwc3_generic_runtime_idle(struct device *dev)
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{
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return dwc3_runtime_idle(dev_get_drvdata(dev));
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}
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static const struct dev_pm_ops dwc3_generic_dev_pm_ops = {
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SYSTEM_SLEEP_PM_OPS(dwc3_generic_suspend, dwc3_generic_resume)
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RUNTIME_PM_OPS(dwc3_generic_runtime_suspend, dwc3_generic_runtime_resume,
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dwc3_generic_runtime_idle)
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};
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static const struct of_device_id dwc3_generic_of_match[] = {
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{ .compatible = "spacemit,k1-dwc3", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, dwc3_generic_of_match);
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static struct platform_driver dwc3_generic_driver = {
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.probe = dwc3_generic_probe,
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.remove = dwc3_generic_remove,
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.driver = {
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.name = "dwc3-generic-plat",
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.of_match_table = dwc3_generic_of_match,
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.pm = pm_ptr(&dwc3_generic_dev_pm_ops),
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},
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};
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module_platform_driver(dwc3_generic_driver);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("DesignWare USB3 generic platform driver");

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