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hoshinolinajannau
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drm/asahi: mmu: UAT change for rust page table rewrite
Originally from: arm64: dts: apple: Remove no-map from pagetables region This should still be compatible with older kernels, since this region is always mapped cached. Signed-off-by: Asahi Lina <lina@asahilina.net>
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Lines changed: 1 addition & 20 deletions

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drivers/gpu/drm/asahi/mmu.rs

Lines changed: 1 addition & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
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//! to currently active GPU VM contexts, as well as the individual `Vm` operations to map and
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//! unmap buffer objects into a single user or kernel address space.
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//!
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//! The actual page table management is delegated to the common kernel `io_pgtable` code.
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//! The actual page table management is in the `pt` module.
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use core::fmt::Debug;
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use core::mem::size_of;
@@ -52,23 +52,6 @@ const UAT_USER_CTX_START: usize = 1;
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/// Number of available user contexts
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const UAT_USER_CTX: usize = UAT_NUM_CTX - UAT_USER_CTX_START;
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/// Number of bits in a page offset.
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pub(crate) const UAT_PGBIT: usize = 14;
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/// UAT page size.
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pub(crate) const UAT_PGSZ: usize = 1 << UAT_PGBIT;
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/// UAT page offset mask.
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pub(crate) const UAT_PGMSK: usize = UAT_PGSZ - 1;
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type Pte = AtomicU64;
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/// Number of PTEs per page.
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const UAT_NPTE: usize = UAT_PGSZ / size_of::<Pte>();
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/// UAT input address space (user)
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pub(crate) const UAT_IAS: usize = 39;
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/// "Fake" kernel UAT input address space (one page level lower)
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pub(crate) const UAT_IAS_KERN: usize = 36;
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/// Lower/user base VA
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pub(crate) const IOVA_USER_BASE: u64 = UAT_PGSZ as u64;
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/// Lower/user top VA
@@ -88,8 +71,6 @@ const IOVA_KERN_RANGE: Range<u64> = IOVA_KERN_BASE..IOVA_KERN_TOP;
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const TTBR_VALID: u64 = 0x1; // BIT(0)
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const TTBR_ASID_SHIFT: usize = 48;
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const PTE_TABLE: u64 = 0x3; // BIT(0) | BIT(1)
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/// Address of a special dummy page?
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//const IOVA_UNK_PAGE: u64 = 0x6f_ffff8000;
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pub(crate) const IOVA_UNK_PAGE: u64 = IOVA_USER_TOP - 2 * UAT_PGSZ as u64;

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