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clk: mediatek: Add MT8196 disp0 clock support
Add support for the MT8196 disp0 clock controller, which provides clock gate control for the display system. It is integrated with the mtk-mmsys driver, which registers the disp0 clock driver via platform_device_register_data(). Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Laura Nao <laura.nao@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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‎drivers/clk/mediatek/Kconfig‎

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@@ -1038,6 +1038,13 @@ config COMMON_CLK_MT8196_MFGCFG
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help
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This driver supports MediaTek MT8196 mfgcfg clocks.
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config COMMON_CLK_MT8196_MMSYS
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tristate "Clock driver for MediaTek MT8196 mmsys"
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depends on COMMON_CLK_MT8196
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default m
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help
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This driver supports MediaTek MT8196 mmsys clocks.
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config COMMON_CLK_MT8196_PEXTPSYS
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tristate "Clock driver for MediaTek MT8196 pextpsys"
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depends on COMMON_CLK_MT8196

‎drivers/clk/mediatek/Makefile‎

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@@ -157,6 +157,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
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obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o
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obj-$(CONFIG_COMMON_CLK_MT8196_MDPSYS) += clk-mt8196-mdpsys.o
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obj-$(CONFIG_COMMON_CLK_MT8196_MFGCFG) += clk-mt8196-mfg.o
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obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o
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obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o
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obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o
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obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o

‎drivers/clk/mediatek/clk-mt8196-disp0.c‎

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2025 MediaTek Inc.
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* Guangjie Song <guangjie.song@mediatek.com>
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* Copyright (c) 2025 Collabora Ltd.
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* Laura Nao <laura.nao@collabora.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8196-clock.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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static const struct mtk_gate_regs mm0_cg_regs = {
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.set_ofs = 0x104,
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.clr_ofs = 0x108,
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.sta_ofs = 0x100,
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};
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static const struct mtk_gate_regs mm0_hwv_regs = {
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.set_ofs = 0x0020,
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.clr_ofs = 0x0024,
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.sta_ofs = 0x2c10,
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};
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static const struct mtk_gate_regs mm1_cg_regs = {
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.set_ofs = 0x114,
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.clr_ofs = 0x118,
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.sta_ofs = 0x110,
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};
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static const struct mtk_gate_regs mm1_hwv_regs = {
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.set_ofs = 0x0028,
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.clr_ofs = 0x002c,
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.sta_ofs = 0x2c14,
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};
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#define GATE_MM0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mm0_cg_regs, \
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.shift = _shift, \
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.flags = CLK_OPS_PARENT_ENABLE, \
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.ops = &mtk_clk_gate_ops_setclr,\
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}
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#define GATE_HWV_MM0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mm0_cg_regs, \
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.hwv_regs = &mm0_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr, \
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.flags = CLK_OPS_PARENT_ENABLE \
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}
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#define GATE_MM1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mm1_cg_regs, \
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.shift = _shift, \
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.flags = CLK_OPS_PARENT_ENABLE, \
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.ops = &mtk_clk_gate_ops_setclr,\
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}
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#define GATE_HWV_MM1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mm1_cg_regs, \
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.hwv_regs = &mm1_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr, \
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.flags = CLK_OPS_PARENT_ENABLE, \
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}
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static const struct mtk_gate mm_clks[] = {
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/* MM0 */
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GATE_HWV_MM0(CLK_MM_CONFIG, "mm_config", "disp", 0),
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GATE_HWV_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "disp", 1),
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GATE_HWV_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "disp", 2),
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GATE_HWV_MM0(CLK_MM_DISP_AAL1, "mm_disp_aal1", "disp", 3),
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GATE_MM0(CLK_MM_DISP_C3D0, "mm_disp_c3d0", "disp", 4),
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GATE_MM0(CLK_MM_DISP_C3D1, "mm_disp_c3d1", "disp", 5),
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GATE_MM0(CLK_MM_DISP_C3D2, "mm_disp_c3d2", "disp", 6),
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GATE_MM0(CLK_MM_DISP_C3D3, "mm_disp_c3d3", "disp", 7),
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GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "disp", 8),
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GATE_MM0(CLK_MM_DISP_CCORR1, "mm_disp_ccorr1", "disp", 9),
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GATE_MM0(CLK_MM_DISP_CCORR2, "mm_disp_ccorr2", "disp", 10),
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GATE_MM0(CLK_MM_DISP_CCORR3, "mm_disp_ccorr3", "disp", 11),
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GATE_MM0(CLK_MM_DISP_CHIST0, "mm_disp_chist0", "disp", 12),
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GATE_MM0(CLK_MM_DISP_CHIST1, "mm_disp_chist1", "disp", 13),
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GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "disp", 14),
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GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "disp", 15),
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GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "disp", 16),
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GATE_MM0(CLK_MM_DISP_DITHER1, "mm_disp_dither1", "disp", 17),
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GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC0, "mm_disp_dli_async0", "disp", 18),
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GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC1, "mm_disp_dli_async1", "disp", 19),
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GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC2, "mm_disp_dli_async2", "disp", 20),
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GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC3, "mm_disp_dli_async3", "disp", 21),
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GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC4, "mm_disp_dli_async4", "disp", 22),
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GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC5, "mm_disp_dli_async5", "disp", 23),
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GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC6, "mm_disp_dli_async6", "disp", 24),
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GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC7, "mm_disp_dli_async7", "disp", 25),
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GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC8, "mm_disp_dli_async8", "disp", 26),
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GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC9, "mm_disp_dli_async9", "disp", 27),
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GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC10, "mm_disp_dli_async10", "disp", 28),
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GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC11, "mm_disp_dli_async11", "disp", 29),
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GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC12, "mm_disp_dli_async12", "disp", 30),
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GATE_HWV_MM0(CLK_MM_DISP_DLI_ASYNC13, "mm_disp_dli_async13", "disp", 31),
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/* MM1 */
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GATE_HWV_MM1(CLK_MM_DISP_DLI_ASYNC14, "mm_disp_dli_async14", "disp", 0),
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GATE_HWV_MM1(CLK_MM_DISP_DLI_ASYNC15, "mm_disp_dli_async15", "disp", 1),
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GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC0, "mm_disp_dlo_async0", "disp", 2),
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GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC1, "mm_disp_dlo_async1", "disp", 3),
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GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC2, "mm_disp_dlo_async2", "disp", 4),
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GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC3, "mm_disp_dlo_async3", "disp", 5),
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GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC4, "mm_disp_dlo_async4", "disp", 6),
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GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC5, "mm_disp_dlo_async5", "disp", 7),
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GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC6, "mm_disp_dlo_async6", "disp", 8),
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GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC7, "mm_disp_dlo_async7", "disp", 9),
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GATE_HWV_MM1(CLK_MM_DISP_DLO_ASYNC8, "mm_disp_dlo_async8", "disp", 10),
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GATE_MM1(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "disp", 11),
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GATE_MM1(CLK_MM_DISP_GAMMA1, "mm_disp_gamma1", "disp", 12),
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GATE_MM1(CLK_MM_MDP_AAL0, "mm_mdp_aal0", "disp", 13),
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GATE_MM1(CLK_MM_MDP_AAL1, "mm_mdp_aal1", "disp", 14),
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GATE_HWV_MM1(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "disp", 15),
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GATE_HWV_MM1(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "disp", 16),
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GATE_HWV_MM1(CLK_MM_DISP_POSTMASK1, "mm_disp_postmask1", "disp", 17),
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GATE_HWV_MM1(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "disp", 18),
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GATE_HWV_MM1(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "disp", 19),
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GATE_HWV_MM1(CLK_MM_DISP_SPR0, "mm_disp_spr0", "disp", 20),
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GATE_MM1(CLK_MM_DISP_TDSHP0, "mm_disp_tdshp0", "disp", 21),
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GATE_MM1(CLK_MM_DISP_TDSHP1, "mm_disp_tdshp1", "disp", 22),
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GATE_HWV_MM1(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp", 23),
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GATE_HWV_MM1(CLK_MM_DISP_Y2R0, "mm_disp_y2r0", "disp", 24),
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GATE_HWV_MM1(CLK_MM_SMI_SUB_COMM0, "mm_ssc", "disp", 25),
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GATE_HWV_MM1(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "disp", 26),
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};
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static const struct mtk_clk_desc mm_mcd = {
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.clks = mm_clks,
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.num_clks = ARRAY_SIZE(mm_clks),
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};
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static const struct platform_device_id clk_mt8196_disp0_id_table[] = {
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{ .name = "clk-mt8196-disp0", .driver_data = (kernel_ulong_t)&mm_mcd },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(platform, clk_mt8196_disp0_id_table);
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static struct platform_driver clk_mt8196_disp0_drv = {
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.probe = mtk_clk_pdev_probe,
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.remove = mtk_clk_pdev_remove,
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.driver = {
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.name = "clk-mt8196-disp0",
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},
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.id_table = clk_mt8196_disp0_id_table,
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};
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module_platform_driver(clk_mt8196_disp0_drv);
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MODULE_DESCRIPTION("MediaTek MT8196 disp0 clocks driver");
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MODULE_LICENSE("GPL");

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