|
165 | 165 | status = "disabled"; |
166 | 166 | }; |
167 | 167 |
|
| 168 | + dsia: dsi@54300000 { |
| 169 | + compatible = "nvidia,tegra124-dsi"; |
| 170 | + reg = <0x0 0x54300000 0x0 0x00040000>; |
| 171 | + clocks = <&tegra_car TEGRA124_CLK_DSIA>, |
| 172 | + <&tegra_car TEGRA124_CLK_DSIALP>, |
| 173 | + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; |
| 174 | + clock-names = "dsi", "lp", "parent"; |
| 175 | + resets = <&tegra_car 48>; |
| 176 | + reset-names = "dsi"; |
| 177 | + nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ |
| 178 | + status = "disabled"; |
| 179 | + |
| 180 | + #address-cells = <1>; |
| 181 | + #size-cells = <0>; |
| 182 | + }; |
| 183 | + |
168 | 184 | vic@54340000 { |
169 | 185 | compatible = "nvidia,tegra124-vic"; |
170 | 186 | reg = <0x0 0x54340000 0x0 0x00040000>; |
|
177 | 193 | iommus = <&mc TEGRA_SWGROUP_VIC>; |
178 | 194 | }; |
179 | 195 |
|
| 196 | + dsib: dsi@54400000 { |
| 197 | + compatible = "nvidia,tegra124-dsi"; |
| 198 | + reg = <0x0 0x54400000 0x0 0x00040000>; |
| 199 | + clocks = <&tegra_car TEGRA124_CLK_DSIB>, |
| 200 | + <&tegra_car TEGRA124_CLK_DSIBLP>, |
| 201 | + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; |
| 202 | + clock-names = "dsi", "lp", "parent"; |
| 203 | + resets = <&tegra_car 82>; |
| 204 | + reset-names = "dsi"; |
| 205 | + nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ |
| 206 | + status = "disabled"; |
| 207 | + |
| 208 | + #address-cells = <1>; |
| 209 | + #size-cells = <0>; |
| 210 | + }; |
| 211 | + |
180 | 212 | sor@54540000 { |
181 | 213 | compatible = "nvidia,tegra124-sor"; |
182 | 214 | reg = <0x0 0x54540000 0x0 0x00040000>; |
|
938 | 970 | }; |
939 | 971 | }; |
940 | 972 |
|
| 973 | + mipi: mipi@700e3000 { |
| 974 | + compatible = "nvidia,tegra124-mipi"; |
| 975 | + reg = <0x0 0x700e3000 0x0 0x100>; |
| 976 | + clocks = <&tegra_car TEGRA124_CLK_MIPI_CAL>; |
| 977 | + clock-names = "mipi-cal"; |
| 978 | + #nvidia,mipi-calibrate-cells = <1>; |
| 979 | + }; |
| 980 | + |
941 | 981 | dfll: clock@70110000 { |
942 | 982 | compatible = "nvidia,tegra124-dfll"; |
943 | 983 | reg = <0 0x70110000 0 0x100>, /* DFLL control */ |
|
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