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Lijo Lazaralexdeucher
Lijo Lazar
authored and
alexdeucher
committed
drm/amdgpu: Add a noverbose flag to psp_wait_for
For extended wait with retries on a PSP register value, add a noverbose flag to avoid excessive error messages on each timeout. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent a54e463 commit 9888f73

10 files changed

Lines changed: 130 additions & 118 deletions

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‎drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c‎

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -575,9 +575,11 @@ static int psp_sw_fini(struct amdgpu_ip_block *ip_block)
575575
return 0;
576576
}
577577

578-
int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
579-
uint32_t reg_val, uint32_t mask, bool check_changed)
578+
int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val,
579+
uint32_t mask, uint32_t flags)
580580
{
581+
bool check_changed = flags & PSP_WAITREG_CHANGED;
582+
bool verbose = !(flags & PSP_WAITREG_NOVERBOSE);
581583
uint32_t val;
582584
int i;
583585
struct amdgpu_device *adev = psp->adev;
@@ -597,9 +599,10 @@ int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
597599
udelay(1);
598600
}
599601

600-
dev_err(adev->dev,
601-
"psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x",
602-
reg_index, mask, val, reg_val);
602+
if (verbose)
603+
dev_err(adev->dev,
604+
"psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x",
605+
reg_index, mask, val, reg_val);
603606

604607
return -ETIME;
605608
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -134,6 +134,9 @@ enum psp_reg_prog_id {
134134
PSP_REG_LAST
135135
};
136136

137+
#define PSP_WAITREG_CHANGED BIT(0) /* check if the value has changed */
138+
#define PSP_WAITREG_NOVERBOSE BIT(1) /* No error verbose */
139+
137140
struct psp_funcs {
138141
int (*init_microcode)(struct psp_context *psp);
139142
int (*wait_for_bootloader)(struct psp_context *psp);
@@ -532,8 +535,8 @@ extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
532535
extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
533536
extern const struct amdgpu_ip_block_version psp_v14_0_ip_block;
534537

535-
extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
536-
uint32_t field_val, uint32_t mask, bool check_changed);
538+
int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
539+
uint32_t field_val, uint32_t mask, uint32_t flags);
537540
extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
538541
uint32_t field_val, uint32_t mask, uint32_t msec_timeout);
539542

‎drivers/gpu/drm/amd/amdgpu/psp_v10_0.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,7 @@ static int psp_v10_0_ring_create(struct psp_context *psp,
9494

9595
/* Wait for response flag (bit 31) in C2PMSG_64 */
9696
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
97-
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
97+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
9898

9999
return ret;
100100
}
@@ -115,7 +115,7 @@ static int psp_v10_0_ring_stop(struct psp_context *psp,
115115

116116
/* Wait for response flag (bit 31) in C2PMSG_64 */
117117
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
118-
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
118+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
119119

120120
return ret;
121121
}

‎drivers/gpu/drm/amd/amdgpu/psp_v11_0.c‎

Lines changed: 17 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -152,11 +152,9 @@ static int psp_v11_0_wait_for_bootloader(struct psp_context *psp)
152152
for (retry_loop = 0; retry_loop < 10; retry_loop++) {
153153
/* Wait for bootloader to signify that is
154154
ready having bit 31 of C2PMSG_35 set to 1 */
155-
ret = psp_wait_for(psp,
156-
SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
157-
0x80000000,
158-
0x80000000,
159-
false);
155+
ret = psp_wait_for(
156+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
157+
0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);
160158

161159
if (ret == 0)
162160
return 0;
@@ -252,8 +250,8 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
252250
/* there might be handshake issue with hardware which needs delay */
253251
mdelay(20);
254252
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
255-
RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
256-
0, true);
253+
RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,
254+
PSP_WAITREG_CHANGED);
257255

258256
return ret;
259257
}
@@ -279,11 +277,11 @@ static int psp_v11_0_ring_stop(struct psp_context *psp,
279277
if (amdgpu_sriov_vf(adev))
280278
ret = psp_wait_for(
281279
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
282-
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
280+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
283281
else
284282
ret = psp_wait_for(
285283
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
286-
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
284+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
287285

288286
return ret;
289287
}
@@ -321,13 +319,13 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
321319
/* Wait for response flag (bit 31) in C2PMSG_101 */
322320
ret = psp_wait_for(
323321
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
324-
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
322+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
325323

326324
} else {
327325
/* Wait for sOS ready for ring creation */
328326
ret = psp_wait_for(
329327
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
330-
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
328+
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);
331329
if (ret) {
332330
DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
333331
return ret;
@@ -353,7 +351,7 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
353351
/* Wait for response flag (bit 31) in C2PMSG_64 */
354352
ret = psp_wait_for(
355353
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
356-
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
354+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
357355
}
358356

359357
return ret;
@@ -387,7 +385,7 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp)
387385
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
388386

389387
ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG,
390-
MBOX_TOS_READY_MASK, false);
388+
MBOX_TOS_READY_MASK, 0);
391389

392390
if (ret) {
393391
DRM_INFO("psp is not working correctly before mode1 reset!\n");
@@ -402,7 +400,7 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp)
402400
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
403401

404402
ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK,
405-
false);
403+
0);
406404

407405
if (ret) {
408406
DRM_INFO("psp mode 1 reset failed!\n");
@@ -428,8 +426,9 @@ static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
428426

429427
max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
430428
for (i = 0; i < max_wait; i++) {
431-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
432-
0x80000000, 0x80000000, false);
429+
ret = psp_wait_for(
430+
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
431+
0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);
433432
if (ret == 0)
434433
break;
435434
}
@@ -608,7 +607,7 @@ static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc
608607
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
609608

610609
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
611-
0x80000000, 0x80000000, false);
610+
0x80000000, 0x80000000, 0);
612611
if (ret)
613612
return ret;
614613

@@ -645,7 +644,7 @@ static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
645644
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
646645

647646
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
648-
0x80000000, 0x80000000, false);
647+
0x80000000, 0x80000000, 0);
649648
if (!ret)
650649
*fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36);
651650

‎drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ static int psp_v11_0_8_ring_stop(struct psp_context *psp,
4343
/* Wait for response flag (bit 31) */
4444
ret = psp_wait_for(
4545
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
46-
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
46+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
4747
} else {
4848
/* Write the ring destroy command*/
4949
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
@@ -53,7 +53,7 @@ static int psp_v11_0_8_ring_stop(struct psp_context *psp,
5353
/* Wait for response flag (bit 31) */
5454
ret = psp_wait_for(
5555
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
56-
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
56+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
5757
}
5858

5959
return ret;
@@ -91,13 +91,13 @@ static int psp_v11_0_8_ring_create(struct psp_context *psp,
9191
/* Wait for response flag (bit 31) in C2PMSG_101 */
9292
ret = psp_wait_for(
9393
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
94-
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
94+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
9595

9696
} else {
9797
/* Wait for sOS ready for ring creation */
9898
ret = psp_wait_for(
9999
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
100-
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
100+
MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);
101101
if (ret) {
102102
DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
103103
return ret;
@@ -123,7 +123,7 @@ static int psp_v11_0_8_ring_create(struct psp_context *psp,
123123
/* Wait for response flag (bit 31) in C2PMSG_64 */
124124
ret = psp_wait_for(
125125
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
126-
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
126+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
127127
}
128128

129129
return ret;

‎drivers/gpu/drm/amd/amdgpu/psp_v12_0.c‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,7 @@ static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
8282

8383
/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
8484
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
85-
0x80000000, 0x80000000, false);
85+
0x80000000, 0x80000000, 0);
8686
if (ret)
8787
return ret;
8888

@@ -97,7 +97,7 @@ static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
9797
psp_gfxdrv_command_reg);
9898

9999
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
100-
0x80000000, 0x80000000, false);
100+
0x80000000, 0x80000000, 0);
101101

102102
return ret;
103103
}
@@ -118,7 +118,7 @@ static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
118118

119119
/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
120120
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
121-
0x80000000, 0x80000000, false);
121+
0x80000000, 0x80000000, 0);
122122
if (ret)
123123
return ret;
124124

@@ -133,8 +133,8 @@ static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
133133
psp_gfxdrv_command_reg);
134134

135135
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
136-
RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
137-
0, true);
136+
RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,
137+
PSP_WAITREG_CHANGED);
138138

139139
return ret;
140140
}
@@ -163,7 +163,7 @@ static int psp_v12_0_ring_create(struct psp_context *psp,
163163

164164
/* Wait for response flag (bit 31) in C2PMSG_64 */
165165
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
166-
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
166+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
167167

168168
return ret;
169169
}
@@ -186,11 +186,11 @@ static int psp_v12_0_ring_stop(struct psp_context *psp,
186186
if (amdgpu_sriov_vf(adev))
187187
ret = psp_wait_for(
188188
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
189-
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
189+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
190190
else
191191
ret = psp_wait_for(
192192
psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
193-
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
193+
MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
194194

195195
return ret;
196196
}
@@ -222,7 +222,7 @@ static int psp_v12_0_mode1_reset(struct psp_context *psp)
222222
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
223223

224224
ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG,
225-
MBOX_TOS_READY_MASK, false);
225+
MBOX_TOS_READY_MASK, 0);
226226

227227
if (ret) {
228228
DRM_INFO("psp is not working correctly before mode1 reset!\n");
@@ -237,7 +237,7 @@ static int psp_v12_0_mode1_reset(struct psp_context *psp)
237237
offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
238238

239239
ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK,
240-
false);
240+
0);
241241

242242
if (ret) {
243243
DRM_INFO("psp mode 1 reset failed!\n");

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