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perf vendor events intel: Update arrowlake events from 1.13 to 1.14
The updated events were published in: intel/perfmon@588dd77 Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
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‎tools/perf/pmu-events/arch/x86/arrowlake/cache.json‎

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‎tools/perf/pmu-events/arch/x86/arrowlake/floating-point.json‎

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[
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{
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"BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.",
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"Counter": "0,1,2,3,4,5,6,7",
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"CounterMask": "1",
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"EventCode": "0xcd",
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"EventName": "ARITH.FPDIV_ACTIVE",
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"SampleAfterValue": "1000003",
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"UMask": "0x2",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Cycles when floating-point divide unit is busy executing divide or square root operations.",
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"Counter": "0,1,2,3,4,5,6,7,8,9",
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"UMask": "0x2",
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"Unit": "cpu_lowpower"
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},
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{
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"BriefDescription": "Counts the number of active floating point dividers per cycle in the loop stage.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xcd",
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"EventName": "ARITH.FPDIV_OCCUPANCY",
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"SampleAfterValue": "1000003",
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"UMask": "0x2",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of floating point divider uops executed per cycle.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xcd",
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"EventName": "ARITH.FPDIV_UOPS",
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"SampleAfterValue": "1000003",
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"UMask": "0x8",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts all microcode FP assists.",
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"Counter": "0,1,2,3,4,5,6,7,8,9",
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"UMask": "0x3f",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of uops executed on all floating point ports.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xb2",
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"EventName": "FP_VINT_UOPS_EXECUTED.ALL",
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"SampleAfterValue": "1000003",
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"UMask": "0x1f",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xb2",
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"EventName": "FP_VINT_UOPS_EXECUTED.P0",
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"SampleAfterValue": "1000003",
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"UMask": "0x2",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 1.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xb2",
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"EventName": "FP_VINT_UOPS_EXECUTED.P1",
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"SampleAfterValue": "1000003",
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"UMask": "0x4",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 2.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xb2",
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"EventName": "FP_VINT_UOPS_EXECUTED.P2",
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"SampleAfterValue": "1000003",
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"UMask": "0x8",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 3.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xb2",
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"EventName": "FP_VINT_UOPS_EXECUTED.P3",
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"SampleAfterValue": "1000003",
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"UMask": "0x10",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0, 1, 2, 3.",
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"Counter": "0,1,2,3,4,5,6,7",

‎tools/perf/pmu-events/arch/x86/arrowlake/frontend.json‎

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"UMask": "0x1",
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"Unit": "cpu_lowpower"
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},
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{
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"BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xe6",
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"EventName": "BACLEARS.COND",
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"SampleAfterValue": "200003",
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"UMask": "0x10",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of BACLEARS due to an indirect branch.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xe6",
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"EventName": "BACLEARS.INDIRECT",
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"SampleAfterValue": "200003",
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"UMask": "0x2",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of BACLEARS due to a return branch.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xe6",
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"EventName": "BACLEARS.RETURN",
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"SampleAfterValue": "200003",
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"UMask": "0x8",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xe6",
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"EventName": "BACLEARS.UNCOND",
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"SampleAfterValue": "200003",
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"UMask": "0x4",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
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"Counter": "0,1,2,3,4,5,6,7,8,9",
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"UMask": "0x2",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of times a decode restriction reduces the decode throughput due to wrong instruction length prediction.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xe9",
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"EventName": "DECODE_RESTRICTION.PREDECODE_WRONG",
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"SampleAfterValue": "200003",
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"UMask": "0x1",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "DSB-to-MITE switch true penalty cycles.",
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"Counter": "0,1,2,3,4,5,6,7,8,9",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of cycles that the micro-sequencer is busy.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xe7",
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"EventName": "MS_DECODED.MS_BUSY",
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"SampleAfterValue": "200003",
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"UMask": "0x4",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of cycles that the micro-sequencer is busy.",
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"Counter": "0,1,2,3,4,5,6,7",
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"SampleAfterValue": "1000003",
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"UMask": "0x4",
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"Unit": "cpu_lowpower"
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},
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{
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"BriefDescription": "Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xe7",
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"EventName": "MS_DECODED.MS_ENTRY",
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"SampleAfterValue": "200003",
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"UMask": "0x1",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of times nanocode flow is executed.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xe7",
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"EventName": "MS_DECODED.NANO_CODE",
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"SampleAfterValue": "200003",
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"UMask": "0x2",
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"Unit": "cpu_atom"
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}
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]

‎tools/perf/pmu-events/arch/x86/arrowlake/memory.json‎

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[
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x05",
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"EventName": "LD_HEAD.ANY",
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"SampleAfterValue": "1000003",
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"UMask": "0x7f",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",
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"Counter": "0,1,2,3,4,5,6,7",
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"UMask": "0x81",
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"Unit": "cpu_lowpower"
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},
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to other block cases.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x05",
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"EventName": "LD_HEAD.OTHER",
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"PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to other block cases such as pipeline conflicts, fences, etc.",
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"SampleAfterValue": "1000003",
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"UMask": "0x40",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.",
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"Counter": "0,1,2,3,4,5,6,7",
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"UMask": "0xc0",
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"Unit": "cpu_lowpower"
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},
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a pagewalk.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x05",
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"EventName": "LD_HEAD.PGWALK",
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"SampleAfterValue": "1000003",
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"UMask": "0x20",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.",
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"Counter": "0,1,2,3,4,5,6,7",
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"UMask": "0xa0",
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"Unit": "cpu_lowpower"
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},
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a store address match.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x05",
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"EventName": "LD_HEAD.ST_ADDR",
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"SampleAfterValue": "1000003",
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"UMask": "0x4",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.",
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"Counter": "0,1,2,3,4,5,6,7",
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"UMask": "0x84",
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"Unit": "cpu_lowpower"
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},
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to store data forward block.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x05",
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"EventName": "LD_HEAD.ST_DATA",
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"SampleAfterValue": "1000003",
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"UMask": "0x8",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to request buffers full or lock in progress.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x05",
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"EventName": "LD_HEAD.WCB_FULL",
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"SampleAfterValue": "1000003",
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"UMask": "0x2",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress.",
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"Counter": "0,1,2,3,4,5,6,7",
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"UMask": "0x2",
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"Unit": "cpu_lowpower"
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},
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{
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"BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc3",
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"EventName": "MACHINE_CLEARS.MEMORY_ORDERING_FAST",
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"SampleAfterValue": "20003",
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"UMask": "0x82",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",
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"Counter": "2,3,4,5,6,7,8,9",

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