Skip to content

Commit 9bada5f

Browse files
jbrun3tjbrun3t
committed
clk: amlogic: align s4 and c3 pwm clock descriptions
s4 and c3 follow exactly the same structure when it comes to PWM clocks but differ in the way these clocks are described, for no obvious reason. Align the description of the pwm clocks of these SoCs with the composite clock helpers. Reviewed-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-11-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
1 parent 955e18b commit 9bada5f

2 files changed

Lines changed: 103 additions & 609 deletions

File tree

‎drivers/clk/meson/c3-peripherals.c‎

Lines changed: 64 additions & 140 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,15 @@
4848
#define SPIFC_CLK_CTRL 0x1a0
4949
#define NNA_CLK_CTRL 0x220
5050

51+
#define C3_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \
52+
MESON_COMP_SEL(c3_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0)
53+
54+
#define C3_COMP_DIV(_name, _reg, _shift, _width) \
55+
MESON_COMP_DIV(c3_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT)
56+
57+
#define C3_COMP_GATE(_name, _reg, _bit) \
58+
MESON_COMP_GATE(c3_, _name, _reg, _bit, CLK_SET_RATE_PARENT)
59+
5160
static struct clk_regmap c3_rtc_xtal_clkin = {
5261
.data = &(struct clk_regmap_gate_data) {
5362
.offset = RTC_BY_OSCIN_CTRL0,
@@ -512,146 +521,61 @@ static const struct clk_parent_data c3_pwm_parents[] = {
512521
{ .fw_name = "fdiv3" }
513522
};
514523

515-
#define C3_PWM_CLK_MUX(_name, _reg, _shift) { \
516-
.data = &(struct clk_regmap_mux_data) { \
517-
.offset = _reg, \
518-
.mask = 0x3, \
519-
.shift = _shift, \
520-
}, \
521-
.hw.init = &(struct clk_init_data) { \
522-
.name = #_name "_sel", \
523-
.ops = &clk_regmap_mux_ops, \
524-
.parent_data = c3_pwm_parents, \
525-
.num_parents = ARRAY_SIZE(c3_pwm_parents), \
526-
}, \
527-
}
528-
529-
#define C3_PWM_CLK_DIV(_name, _reg, _shift) { \
530-
.data = &(struct clk_regmap_div_data) { \
531-
.offset = _reg, \
532-
.shift = _shift, \
533-
.width = 8, \
534-
}, \
535-
.hw.init = &(struct clk_init_data) { \
536-
.name = #_name "_div", \
537-
.ops = &clk_regmap_divider_ops, \
538-
.parent_names = (const char *[]) { #_name "_sel" },\
539-
.num_parents = 1, \
540-
.flags = CLK_SET_RATE_PARENT, \
541-
}, \
542-
}
543-
544-
#define C3_PWM_CLK_GATE(_name, _reg, _bit) { \
545-
.data = &(struct clk_regmap_gate_data) { \
546-
.offset = _reg, \
547-
.bit_idx = _bit, \
548-
}, \
549-
.hw.init = &(struct clk_init_data) { \
550-
.name = #_name, \
551-
.ops = &clk_regmap_gate_ops, \
552-
.parent_names = (const char *[]) { #_name "_div" },\
553-
.num_parents = 1, \
554-
.flags = CLK_SET_RATE_PARENT, \
555-
}, \
556-
}
557-
558-
static struct clk_regmap c3_pwm_a_sel =
559-
C3_PWM_CLK_MUX(pwm_a, PWM_CLK_AB_CTRL, 9);
560-
static struct clk_regmap c3_pwm_a_div =
561-
C3_PWM_CLK_DIV(pwm_a, PWM_CLK_AB_CTRL, 0);
562-
static struct clk_regmap c3_pwm_a =
563-
C3_PWM_CLK_GATE(pwm_a, PWM_CLK_AB_CTRL, 8);
564-
565-
static struct clk_regmap c3_pwm_b_sel =
566-
C3_PWM_CLK_MUX(pwm_b, PWM_CLK_AB_CTRL, 25);
567-
static struct clk_regmap c3_pwm_b_div =
568-
C3_PWM_CLK_DIV(pwm_b, PWM_CLK_AB_CTRL, 16);
569-
static struct clk_regmap c3_pwm_b =
570-
C3_PWM_CLK_GATE(pwm_b, PWM_CLK_AB_CTRL, 24);
571-
572-
static struct clk_regmap c3_pwm_c_sel =
573-
C3_PWM_CLK_MUX(pwm_c, PWM_CLK_CD_CTRL, 9);
574-
static struct clk_regmap c3_pwm_c_div =
575-
C3_PWM_CLK_DIV(pwm_c, PWM_CLK_CD_CTRL, 0);
576-
static struct clk_regmap c3_pwm_c =
577-
C3_PWM_CLK_GATE(pwm_c, PWM_CLK_CD_CTRL, 8);
578-
579-
static struct clk_regmap c3_pwm_d_sel =
580-
C3_PWM_CLK_MUX(pwm_d, PWM_CLK_CD_CTRL, 25);
581-
static struct clk_regmap c3_pwm_d_div =
582-
C3_PWM_CLK_DIV(pwm_d, PWM_CLK_CD_CTRL, 16);
583-
static struct clk_regmap c3_pwm_d =
584-
C3_PWM_CLK_GATE(pwm_d, PWM_CLK_CD_CTRL, 24);
585-
586-
static struct clk_regmap c3_pwm_e_sel =
587-
C3_PWM_CLK_MUX(pwm_e, PWM_CLK_EF_CTRL, 9);
588-
static struct clk_regmap c3_pwm_e_div =
589-
C3_PWM_CLK_DIV(pwm_e, PWM_CLK_EF_CTRL, 0);
590-
static struct clk_regmap c3_pwm_e =
591-
C3_PWM_CLK_GATE(pwm_e, PWM_CLK_EF_CTRL, 8);
592-
593-
static struct clk_regmap c3_pwm_f_sel =
594-
C3_PWM_CLK_MUX(pwm_f, PWM_CLK_EF_CTRL, 25);
595-
static struct clk_regmap c3_pwm_f_div =
596-
C3_PWM_CLK_DIV(pwm_f, PWM_CLK_EF_CTRL, 16);
597-
static struct clk_regmap c3_pwm_f =
598-
C3_PWM_CLK_GATE(pwm_f, PWM_CLK_EF_CTRL, 24);
599-
600-
static struct clk_regmap c3_pwm_g_sel =
601-
C3_PWM_CLK_MUX(pwm_g, PWM_CLK_GH_CTRL, 9);
602-
static struct clk_regmap c3_pwm_g_div =
603-
C3_PWM_CLK_DIV(pwm_g, PWM_CLK_GH_CTRL, 0);
604-
static struct clk_regmap c3_pwm_g =
605-
C3_PWM_CLK_GATE(pwm_g, PWM_CLK_GH_CTRL, 8);
606-
607-
static struct clk_regmap c3_pwm_h_sel =
608-
C3_PWM_CLK_MUX(pwm_h, PWM_CLK_GH_CTRL, 25);
609-
static struct clk_regmap c3_pwm_h_div =
610-
C3_PWM_CLK_DIV(pwm_h, PWM_CLK_GH_CTRL, 16);
611-
static struct clk_regmap c3_pwm_h =
612-
C3_PWM_CLK_GATE(pwm_h, PWM_CLK_GH_CTRL, 24);
613-
614-
static struct clk_regmap c3_pwm_i_sel =
615-
C3_PWM_CLK_MUX(pwm_i, PWM_CLK_IJ_CTRL, 9);
616-
static struct clk_regmap c3_pwm_i_div =
617-
C3_PWM_CLK_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0);
618-
static struct clk_regmap c3_pwm_i =
619-
C3_PWM_CLK_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8);
620-
621-
static struct clk_regmap c3_pwm_j_sel =
622-
C3_PWM_CLK_MUX(pwm_j, PWM_CLK_IJ_CTRL, 25);
623-
static struct clk_regmap c3_pwm_j_div =
624-
C3_PWM_CLK_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16);
625-
static struct clk_regmap c3_pwm_j =
626-
C3_PWM_CLK_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24);
627-
628-
static struct clk_regmap c3_pwm_k_sel =
629-
C3_PWM_CLK_MUX(pwm_k, PWM_CLK_KL_CTRL, 9);
630-
static struct clk_regmap c3_pwm_k_div =
631-
C3_PWM_CLK_DIV(pwm_k, PWM_CLK_KL_CTRL, 0);
632-
static struct clk_regmap c3_pwm_k =
633-
C3_PWM_CLK_GATE(pwm_k, PWM_CLK_KL_CTRL, 8);
634-
635-
static struct clk_regmap c3_pwm_l_sel =
636-
C3_PWM_CLK_MUX(pwm_l, PWM_CLK_KL_CTRL, 25);
637-
static struct clk_regmap c3_pwm_l_div =
638-
C3_PWM_CLK_DIV(pwm_l, PWM_CLK_KL_CTRL, 16);
639-
static struct clk_regmap c3_pwm_l =
640-
C3_PWM_CLK_GATE(pwm_l, PWM_CLK_KL_CTRL, 24);
641-
642-
static struct clk_regmap c3_pwm_m_sel =
643-
C3_PWM_CLK_MUX(pwm_m, PWM_CLK_MN_CTRL, 9);
644-
static struct clk_regmap c3_pwm_m_div =
645-
C3_PWM_CLK_DIV(pwm_m, PWM_CLK_MN_CTRL, 0);
646-
static struct clk_regmap c3_pwm_m =
647-
C3_PWM_CLK_GATE(pwm_m, PWM_CLK_MN_CTRL, 8);
648-
649-
static struct clk_regmap c3_pwm_n_sel =
650-
C3_PWM_CLK_MUX(pwm_n, PWM_CLK_MN_CTRL, 25);
651-
static struct clk_regmap c3_pwm_n_div =
652-
C3_PWM_CLK_DIV(pwm_n, PWM_CLK_MN_CTRL, 16);
653-
static struct clk_regmap c3_pwm_n =
654-
C3_PWM_CLK_GATE(pwm_n, PWM_CLK_MN_CTRL, 24);
524+
static C3_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, c3_pwm_parents);
525+
static C3_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8);
526+
static C3_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8);
527+
528+
static C3_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, c3_pwm_parents);
529+
static C3_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8);
530+
static C3_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24);
531+
532+
static C3_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, c3_pwm_parents);
533+
static C3_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8);
534+
static C3_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8);
535+
536+
static C3_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, c3_pwm_parents);
537+
static C3_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8);
538+
static C3_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24);
539+
540+
static C3_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, c3_pwm_parents);
541+
static C3_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8);
542+
static C3_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8);
543+
544+
static C3_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, c3_pwm_parents);
545+
static C3_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8);
546+
static C3_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24);
547+
548+
static C3_COMP_SEL(pwm_g, PWM_CLK_GH_CTRL, 9, 0x3, c3_pwm_parents);
549+
static C3_COMP_DIV(pwm_g, PWM_CLK_GH_CTRL, 0, 8);
550+
static C3_COMP_GATE(pwm_g, PWM_CLK_GH_CTRL, 8);
551+
552+
static C3_COMP_SEL(pwm_h, PWM_CLK_GH_CTRL, 25, 0x3, c3_pwm_parents);
553+
static C3_COMP_DIV(pwm_h, PWM_CLK_GH_CTRL, 16, 8);
554+
static C3_COMP_GATE(pwm_h, PWM_CLK_GH_CTRL, 24);
555+
556+
static C3_COMP_SEL(pwm_i, PWM_CLK_IJ_CTRL, 9, 0x3, c3_pwm_parents);
557+
static C3_COMP_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0, 8);
558+
static C3_COMP_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8);
559+
560+
static C3_COMP_SEL(pwm_j, PWM_CLK_IJ_CTRL, 25, 0x3, c3_pwm_parents);
561+
static C3_COMP_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16, 8);
562+
static C3_COMP_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24);
563+
564+
static C3_COMP_SEL(pwm_k, PWM_CLK_KL_CTRL, 9, 0x3, c3_pwm_parents);
565+
static C3_COMP_DIV(pwm_k, PWM_CLK_KL_CTRL, 0, 8);
566+
static C3_COMP_GATE(pwm_k, PWM_CLK_KL_CTRL, 8);
567+
568+
static C3_COMP_SEL(pwm_l, PWM_CLK_KL_CTRL, 25, 0x3, c3_pwm_parents);
569+
static C3_COMP_DIV(pwm_l, PWM_CLK_KL_CTRL, 16, 8);
570+
static C3_COMP_GATE(pwm_l, PWM_CLK_KL_CTRL, 24);
571+
572+
static C3_COMP_SEL(pwm_m, PWM_CLK_MN_CTRL, 9, 0x3, c3_pwm_parents);
573+
static C3_COMP_DIV(pwm_m, PWM_CLK_MN_CTRL, 0, 8);
574+
static C3_COMP_GATE(pwm_m, PWM_CLK_MN_CTRL, 8);
575+
576+
static C3_COMP_SEL(pwm_n, PWM_CLK_MN_CTRL, 25, 0x3, c3_pwm_parents);
577+
static C3_COMP_DIV(pwm_n, PWM_CLK_MN_CTRL, 16, 8);
578+
static C3_COMP_GATE(pwm_n, PWM_CLK_MN_CTRL, 24);
655579

656580
static const struct clk_parent_data c3_spicc_parents[] = {
657581
{ .fw_name = "oscin" },

0 commit comments

Comments
 (0)