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thermal/drivers/tegra: Add Tegra114 specific SOCTHERM driver
Add Tegra114 specific SOCTHERM driver. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Link: https://lore.kernel.org/r/20250828055104.8073-6-clamor95@gmail.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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‎drivers/thermal/tegra/Makefile‎

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@@ -4,6 +4,7 @@ obj-$(CONFIG_TEGRA_BPMP_THERMAL) += tegra-bpmp-thermal.o
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obj-$(CONFIG_TEGRA30_TSENSOR) += tegra30-tsensor.o
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tegra-soctherm-y := soctherm.o soctherm-fuse.o
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tegra-soctherm-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114-soctherm.o
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tegra-soctherm-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124-soctherm.o
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tegra-soctherm-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-soctherm.o
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tegra-soctherm-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-soctherm.o

‎drivers/thermal/tegra/soctherm.c‎

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@@ -31,6 +31,7 @@
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#include <linux/reset.h>
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#include <linux/thermal.h>
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#include <dt-bindings/thermal/tegra114-soctherm.h>
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#include <dt-bindings/thermal/tegra124-soctherm.h>
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#include "../thermal_core.h"
@@ -357,6 +358,12 @@ struct soctherm_oc_irq_chip_data {
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static struct soctherm_oc_irq_chip_data soc_irq_cdata;
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/* Ensure that TEGRA114_* and TEGRA124_* counterparts are equal */
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static_assert(TEGRA114_SOCTHERM_SENSOR_CPU == TEGRA124_SOCTHERM_SENSOR_CPU);
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static_assert(TEGRA114_SOCTHERM_SENSOR_MEM == TEGRA124_SOCTHERM_SENSOR_MEM);
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static_assert(TEGRA114_SOCTHERM_SENSOR_GPU == TEGRA124_SOCTHERM_SENSOR_GPU);
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static_assert(TEGRA114_SOCTHERM_SENSOR_PLLX == TEGRA124_SOCTHERM_SENSOR_PLLX);
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/**
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* ccroc_writel() - writes a value to a CCROC register
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* @ts: pointer to a struct tegra_soctherm
@@ -2045,6 +2052,12 @@ static void soctherm_init(struct platform_device *pdev)
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}
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static const struct of_device_id tegra_soctherm_of_match[] = {
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#ifdef CONFIG_ARCH_TEGRA_114_SOC
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{
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.compatible = "nvidia,tegra114-soctherm",
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.data = &tegra114_soctherm,
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},
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#endif
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#ifdef CONFIG_ARCH_TEGRA_124_SOC
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{
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.compatible = "nvidia,tegra124-soctherm",

‎drivers/thermal/tegra/soctherm.h‎

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@@ -142,6 +142,10 @@ int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor,
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const struct tsensor_shared_calib *shared,
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u32 *calib);
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#ifdef CONFIG_ARCH_TEGRA_114_SOC
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extern const struct tegra_soctherm_soc tegra114_soctherm;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_124_SOC
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extern const struct tegra_soctherm_soc tegra124_soctherm;
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#endif

‎drivers/thermal/tegra/tegra114-soctherm.c‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2024, Svyatoslav Ryhel <clamor95@gmail.com>
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/thermal/tegra114-soctherm.h>
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#include "soctherm.h"
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#define TEGRA114_THERMTRIP_ANY_EN_MASK (0x1 << 28)
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#define TEGRA114_THERMTRIP_MEM_EN_MASK (0x1 << 27)
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#define TEGRA114_THERMTRIP_GPU_EN_MASK (0x1 << 26)
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#define TEGRA114_THERMTRIP_CPU_EN_MASK (0x1 << 25)
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#define TEGRA114_THERMTRIP_TSENSE_EN_MASK (0x1 << 24)
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#define TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK (0xff << 16)
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#define TEGRA114_THERMTRIP_CPU_THRESH_MASK (0xff << 8)
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#define TEGRA114_THERMTRIP_TSENSE_THRESH_MASK 0xff
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#define TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK (0xff << 17)
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#define TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK (0xff << 9)
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#define TEGRA114_THRESH_GRAIN 1000
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#define TEGRA114_BPTT 8
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static const struct tegra_tsensor_configuration tegra114_tsensor_config = {
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.tall = 16300,
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.tiddq_en = 1,
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.ten_count = 1,
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.tsample = 163,
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.tsample_ate = 655,
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};
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static const struct tegra_tsensor_group tegra114_tsensor_group_cpu = {
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.id = TEGRA114_SOCTHERM_SENSOR_CPU,
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.name = "cpu",
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.sensor_temp_offset = SENSOR_TEMP1,
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.sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
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.pdiv = 10,
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.pdiv_ate = 10,
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.pdiv_mask = SENSOR_PDIV_CPU_MASK,
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.pllx_hotspot_diff = 6,
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.pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
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.thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK,
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.thermtrip_enable_mask = TEGRA114_THERMTRIP_CPU_EN_MASK,
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.thermtrip_threshold_mask = TEGRA114_THERMTRIP_CPU_THRESH_MASK,
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.thermctl_isr_mask = THERM_IRQ_CPU_MASK,
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.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
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.thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK,
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.thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK,
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};
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static const struct tegra_tsensor_group tegra114_tsensor_group_gpu = {
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.id = TEGRA114_SOCTHERM_SENSOR_GPU,
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.name = "gpu",
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.sensor_temp_offset = SENSOR_TEMP1,
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.sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
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.pdiv = 10,
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.pdiv_ate = 10,
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.pdiv_mask = SENSOR_PDIV_GPU_MASK,
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.pllx_hotspot_diff = 6,
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.pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
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.thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK,
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.thermtrip_enable_mask = TEGRA114_THERMTRIP_GPU_EN_MASK,
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.thermtrip_threshold_mask = TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK,
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.thermctl_isr_mask = THERM_IRQ_GPU_MASK,
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.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
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.thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK,
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.thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK,
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};
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static const struct tegra_tsensor_group tegra114_tsensor_group_pll = {
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.id = TEGRA114_SOCTHERM_SENSOR_PLLX,
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.name = "pll",
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.sensor_temp_offset = SENSOR_TEMP2,
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.sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
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.pdiv = 10,
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.pdiv_ate = 10,
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.pdiv_mask = SENSOR_PDIV_PLLX_MASK,
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.thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK,
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.thermtrip_enable_mask = TEGRA114_THERMTRIP_TSENSE_EN_MASK,
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.thermtrip_threshold_mask = TEGRA114_THERMTRIP_TSENSE_THRESH_MASK,
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.thermctl_isr_mask = THERM_IRQ_TSENSE_MASK,
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.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
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.thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK,
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.thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK,
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};
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static const struct tegra_tsensor_group tegra114_tsensor_group_mem = {
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.id = TEGRA114_SOCTHERM_SENSOR_MEM,
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.name = "mem",
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.sensor_temp_offset = SENSOR_TEMP2,
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.sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
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.pdiv = 10,
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.pdiv_ate = 10,
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.pdiv_mask = SENSOR_PDIV_MEM_MASK,
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.pllx_hotspot_diff = 0,
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.pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
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.thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK,
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.thermtrip_enable_mask = TEGRA114_THERMTRIP_MEM_EN_MASK,
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.thermtrip_threshold_mask = TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK,
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.thermctl_isr_mask = THERM_IRQ_MEM_MASK,
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.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM,
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.thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK,
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.thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK,
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};
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static const struct tegra_tsensor_group *tegra114_tsensor_groups[] = {
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&tegra114_tsensor_group_cpu,
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&tegra114_tsensor_group_gpu,
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&tegra114_tsensor_group_pll,
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&tegra114_tsensor_group_mem,
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};
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static const struct tegra_tsensor tegra114_tsensors[] = {
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{
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.name = "cpu0",
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.base = 0xc0,
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.config = &tegra114_tsensor_config,
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.calib_fuse_offset = 0x098,
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.fuse_corr_alpha = 1196400,
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.fuse_corr_beta = -13600000,
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.group = &tegra114_tsensor_group_cpu,
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}, {
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.name = "cpu1",
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.base = 0xe0,
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.config = &tegra114_tsensor_config,
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.calib_fuse_offset = 0x084,
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.fuse_corr_alpha = 1196400,
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.fuse_corr_beta = -13600000,
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.group = &tegra114_tsensor_group_cpu,
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}, {
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.name = "cpu2",
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.base = 0x100,
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.config = &tegra114_tsensor_config,
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.calib_fuse_offset = 0x088,
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.fuse_corr_alpha = 1196400,
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.fuse_corr_beta = -13600000,
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.group = &tegra114_tsensor_group_cpu,
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}, {
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.name = "cpu3",
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.base = 0x120,
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.config = &tegra114_tsensor_config,
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.calib_fuse_offset = 0x12c,
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.fuse_corr_alpha = 1196400,
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.fuse_corr_beta = -13600000,
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.group = &tegra114_tsensor_group_cpu,
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}, {
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.name = "mem0",
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.base = 0x140,
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.config = &tegra114_tsensor_config,
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.calib_fuse_offset = 0x158,
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.fuse_corr_alpha = 1000000,
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.fuse_corr_beta = 0,
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.group = &tegra114_tsensor_group_mem,
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}, {
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.name = "mem1",
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.base = 0x160,
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.config = &tegra114_tsensor_config,
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.calib_fuse_offset = 0x15c,
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.fuse_corr_alpha = 1000000,
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.fuse_corr_beta = 0,
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.group = &tegra114_tsensor_group_mem,
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}, {
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.name = "gpu",
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.base = 0x180,
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.config = &tegra114_tsensor_config,
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.calib_fuse_offset = 0x154,
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.fuse_corr_alpha = 1124500,
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.fuse_corr_beta = -9793100,
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.group = &tegra114_tsensor_group_gpu,
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}, {
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.name = "pllx",
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.base = 0x1a0,
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.config = &tegra114_tsensor_config,
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.calib_fuse_offset = 0x160,
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.fuse_corr_alpha = 1224200,
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.fuse_corr_beta = -14665000,
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.group = &tegra114_tsensor_group_pll,
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},
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};
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static const struct tegra_soctherm_fuse tegra114_soctherm_fuse = {
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.fuse_base_cp_mask = 0x3ff,
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.fuse_base_cp_shift = 0,
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.fuse_shift_cp_mask = 0x3f << 10,
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.fuse_shift_cp_shift = 10,
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.fuse_base_ft_mask = 0x7ff << 16,
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.fuse_base_ft_shift = 16,
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.fuse_shift_ft_mask = 0x1f << 27,
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.fuse_shift_ft_shift = 27,
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.fuse_common_reg = FUSE_VSENSOR_CALIB,
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.fuse_spare_realignment = 0,
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.nominal_calib_ft = 90,
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};
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const struct tegra_soctherm_soc tegra114_soctherm = {
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.tsensors = tegra114_tsensors,
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.num_tsensors = ARRAY_SIZE(tegra114_tsensors),
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.ttgs = tegra114_tsensor_groups,
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.num_ttgs = ARRAY_SIZE(tegra114_tsensor_groups),
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.tfuse = &tegra114_soctherm_fuse,
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.thresh_grain = TEGRA114_THRESH_GRAIN,
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.bptt = TEGRA114_BPTT,
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.use_ccroc = false,
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};

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