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Merge tag 'mtk-dts64-fixes-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into for-next
MediaTek ARM64 DTS fixes for v6.9 This fixes some dts validation issues against bindings for multiple SoCs, GPU voltage constraints for Chromebook devices, missing gce-client-reg on various nodes (performance issues) on MT8183/92/95, and also fixes boot issues on MT8195 when SPMI is built as module. * tag 'mtk-dts64-fixes-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: arm64: dts: mediatek: mt2712: fix validation errors arm64: dts: mediatek: mt7986: prefix BPI-R3 cooling maps with "map-" arm64: dts: mediatek: mt7986: drop invalid thermal block clock arm64: dts: mediatek: mt7986: drop "#reset-cells" from Ethernet controller arm64: dts: mediatek: mt7986: drop invalid properties from ethsys arm64: dts: mediatek: mt7622: drop "reset-names" from thermal block arm64: dts: mediatek: mt7622: fix ethernet controller "compatible" arm64: dts: mediatek: mt7622: fix IR nodename arm64: dts: mediatek: mt7622: fix clock controllers arm64: dts: mediatek: mt8186-corsola: Update min voltage constraint for Vgpu arm64: dts: mediatek: mt8183-kukui: Use default min voltage for MT6358 arm64: dts: mediatek: mt8195-cherry: Update min voltage constraint for MT6315 arm64: dts: mediatek: mt8192-asurada: Update min voltage constraint for MT6315 arm64: dts: mediatek: cherry: Describe CPU supplies arm64: dts: mediatek: mt8195: Add missing gce-client-reg to mutex1 arm64: dts: mediatek: mt8195: Add missing gce-client-reg to mutex arm64: dts: mediatek: mt8195: Add missing gce-client-reg to vpp/vdosys arm64: dts: mediatek: mt8192: Add missing gce-client-reg to mutex arm64: dts: mediatek: mt8183: Add power-domains properity to mfgcfg
2 parents fdabd4b + 3baac72 commit 9e0794a

12 files changed

Lines changed: 70 additions & 41 deletions

‎arch/arm64/boot/dts/mediatek/mt2712-evb.dts‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -129,7 +129,7 @@
129129
};
130130

131131
&pio {
132-
eth_default: eth_default {
132+
eth_default: eth-default-pins {
133133
tx_pins {
134134
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>,
135135
<MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>,
@@ -156,7 +156,7 @@
156156
};
157157
};
158158

159-
eth_sleep: eth_sleep {
159+
eth_sleep: eth-sleep-pins {
160160
tx_pins {
161161
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>,
162162
<MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>,
@@ -182,14 +182,14 @@
182182
};
183183
};
184184

185-
usb0_id_pins_float: usb0_iddig {
185+
usb0_id_pins_float: usb0-iddig-pins {
186186
pins_iddig {
187187
pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>;
188188
bias-pull-up;
189189
};
190190
};
191191

192-
usb1_id_pins_float: usb1_iddig {
192+
usb1_id_pins_float: usb1-iddig-pins {
193193
pins_iddig {
194194
pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>;
195195
bias-pull-up;

‎arch/arm64/boot/dts/mediatek/mt2712e.dtsi‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -249,10 +249,11 @@
249249
#clock-cells = <1>;
250250
};
251251

252-
infracfg: syscon@10001000 {
252+
infracfg: clock-controller@10001000 {
253253
compatible = "mediatek,mt2712-infracfg", "syscon";
254254
reg = <0 0x10001000 0 0x1000>;
255255
#clock-cells = <1>;
256+
#reset-cells = <1>;
256257
};
257258

258259
pericfg: syscon@10003000 {

‎arch/arm64/boot/dts/mediatek/mt7622.dtsi‎

Lines changed: 14 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -252,7 +252,7 @@
252252
clock-names = "hif_sel";
253253
};
254254

255-
cir: cir@10009000 {
255+
cir: ir-receiver@10009000 {
256256
compatible = "mediatek,mt7622-cir";
257257
reg = <0 0x10009000 0 0x1000>;
258258
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
@@ -283,16 +283,14 @@
283283
};
284284
};
285285

286-
apmixedsys: apmixedsys@10209000 {
287-
compatible = "mediatek,mt7622-apmixedsys",
288-
"syscon";
286+
apmixedsys: clock-controller@10209000 {
287+
compatible = "mediatek,mt7622-apmixedsys";
289288
reg = <0 0x10209000 0 0x1000>;
290289
#clock-cells = <1>;
291290
};
292291

293-
topckgen: topckgen@10210000 {
294-
compatible = "mediatek,mt7622-topckgen",
295-
"syscon";
292+
topckgen: clock-controller@10210000 {
293+
compatible = "mediatek,mt7622-topckgen";
296294
reg = <0 0x10210000 0 0x1000>;
297295
#clock-cells = <1>;
298296
};
@@ -515,7 +513,6 @@
515513
<&pericfg CLK_PERI_AUXADC_PD>;
516514
clock-names = "therm", "auxadc";
517515
resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
518-
reset-names = "therm";
519516
mediatek,auxadc = <&auxadc>;
520517
mediatek,apmixedsys = <&apmixedsys>;
521518
nvmem-cells = <&thermal_calibration>;
@@ -734,9 +731,8 @@
734731
power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
735732
};
736733

737-
ssusbsys: ssusbsys@1a000000 {
738-
compatible = "mediatek,mt7622-ssusbsys",
739-
"syscon";
734+
ssusbsys: clock-controller@1a000000 {
735+
compatible = "mediatek,mt7622-ssusbsys";
740736
reg = <0 0x1a000000 0 0x1000>;
741737
#clock-cells = <1>;
742738
#reset-cells = <1>;
@@ -793,9 +789,8 @@
793789
};
794790
};
795791

796-
pciesys: pciesys@1a100800 {
797-
compatible = "mediatek,mt7622-pciesys",
798-
"syscon";
792+
pciesys: clock-controller@1a100800 {
793+
compatible = "mediatek,mt7622-pciesys";
799794
reg = <0 0x1a100800 0 0x1000>;
800795
#clock-cells = <1>;
801796
#reset-cells = <1>;
@@ -921,12 +916,13 @@
921916
};
922917
};
923918

924-
hifsys: syscon@1af00000 {
925-
compatible = "mediatek,mt7622-hifsys", "syscon";
919+
hifsys: clock-controller@1af00000 {
920+
compatible = "mediatek,mt7622-hifsys";
926921
reg = <0 0x1af00000 0 0x70>;
922+
#clock-cells = <1>;
927923
};
928924

929-
ethsys: syscon@1b000000 {
925+
ethsys: clock-controller@1b000000 {
930926
compatible = "mediatek,mt7622-ethsys",
931927
"syscon";
932928
reg = <0 0x1b000000 0 0x1000>;
@@ -966,9 +962,7 @@
966962
};
967963

968964
eth: ethernet@1b100000 {
969-
compatible = "mediatek,mt7622-eth",
970-
"mediatek,mt2701-eth",
971-
"syscon";
965+
compatible = "mediatek,mt7622-eth";
972966
reg = <0 0x1b100000 0 0x20000>;
973967
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
974968
<GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,

‎arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -146,19 +146,19 @@
146146

147147
&cpu_thermal {
148148
cooling-maps {
149-
cpu-active-high {
149+
map-cpu-active-high {
150150
/* active: set fan to cooling level 2 */
151151
cooling-device = <&fan 2 2>;
152152
trip = <&cpu_trip_active_high>;
153153
};
154154

155-
cpu-active-med {
155+
map-cpu-active-med {
156156
/* active: set fan to cooling level 1 */
157157
cooling-device = <&fan 1 1>;
158158
trip = <&cpu_trip_active_med>;
159159
};
160160

161-
cpu-active-low {
161+
map-cpu-active-low {
162162
/* active: set fan to cooling level 0 */
163163
cooling-device = <&fan 0 0>;
164164
trip = <&cpu_trip_active_low>;

‎arch/arm64/boot/dts/mediatek/mt7986a.dtsi‎

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -332,9 +332,8 @@
332332
reg = <0 0x1100c800 0 0x800>;
333333
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
334334
clocks = <&infracfg CLK_INFRA_THERM_CK>,
335-
<&infracfg CLK_INFRA_ADC_26M_CK>,
336-
<&infracfg CLK_INFRA_ADC_FRC_CK>;
337-
clock-names = "therm", "auxadc", "adc_32k";
335+
<&infracfg CLK_INFRA_ADC_26M_CK>;
336+
clock-names = "therm", "auxadc";
338337
nvmem-cells = <&thermal_calibration>;
339338
nvmem-cell-names = "calibration-data";
340339
#thermal-sensor-cells = <1>;
@@ -492,8 +491,6 @@
492491
compatible = "mediatek,mt7986-ethsys",
493492
"syscon";
494493
reg = <0 0x15000000 0 0x1000>;
495-
#address-cells = <1>;
496-
#size-cells = <1>;
497494
#clock-cells = <1>;
498495
#reset-cells = <1>;
499496
};
@@ -556,7 +553,6 @@
556553
<&topckgen CLK_TOP_SGM_325M_SEL>;
557554
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
558555
<&apmixedsys CLK_APMIXED_SGMPLL>;
559-
#reset-cells = <1>;
560556
#address-cells = <1>;
561557
#size-cells = <0>;
562558
mediatek,ethsys = <&ethsys>;

‎arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -433,7 +433,6 @@
433433
};
434434

435435
&mt6358_vgpu_reg {
436-
regulator-min-microvolt = <625000>;
437436
regulator-max-microvolt = <900000>;
438437

439438
regulator-coupled-with = <&mt6358_vsram_gpu_reg>;

‎arch/arm64/boot/dts/mediatek/mt8183.dtsi‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1637,6 +1637,7 @@
16371637
compatible = "mediatek,mt8183-mfgcfg", "syscon";
16381638
reg = <0 0x13000000 0 0x1000>;
16391639
#clock-cells = <1>;
1640+
power-domains = <&spm MT8183_POWER_DOMAIN_MFG_ASYNC>;
16401641
};
16411642

16421643
gpu: gpu@13040000 {

‎arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1296,7 +1296,7 @@
12961296
* regulator coupling requirements.
12971297
*/
12981298
regulator-name = "ppvar_dvdd_vgpu";
1299-
regulator-min-microvolt = <600000>;
1299+
regulator-min-microvolt = <500000>;
13001300
regulator-max-microvolt = <950000>;
13011301
regulator-ramp-delay = <6250>;
13021302
regulator-enable-ramp-delay = <200>;

‎arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1421,7 +1421,7 @@
14211421
mt6315_6_vbuck1: vbuck1 {
14221422
regulator-compatible = "vbuck1";
14231423
regulator-name = "Vbcpu";
1424-
regulator-min-microvolt = <300000>;
1424+
regulator-min-microvolt = <400000>;
14251425
regulator-max-microvolt = <1193750>;
14261426
regulator-enable-ramp-delay = <256>;
14271427
regulator-allowed-modes = <0 1 2>;
@@ -1431,7 +1431,7 @@
14311431
mt6315_6_vbuck3: vbuck3 {
14321432
regulator-compatible = "vbuck3";
14331433
regulator-name = "Vlcpu";
1434-
regulator-min-microvolt = <300000>;
1434+
regulator-min-microvolt = <400000>;
14351435
regulator-max-microvolt = <1193750>;
14361436
regulator-enable-ramp-delay = <256>;
14371437
regulator-allowed-modes = <0 1 2>;
@@ -1448,7 +1448,7 @@
14481448
mt6315_7_vbuck1: vbuck1 {
14491449
regulator-compatible = "vbuck1";
14501450
regulator-name = "Vgpu";
1451-
regulator-min-microvolt = <606250>;
1451+
regulator-min-microvolt = <400000>;
14521452
regulator-max-microvolt = <800000>;
14531453
regulator-enable-ramp-delay = <256>;
14541454
regulator-allowed-modes = <0 1 2>;

‎arch/arm64/boot/dts/mediatek/mt8192.dtsi‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1464,6 +1464,7 @@
14641464
reg = <0 0x14001000 0 0x1000>;
14651465
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
14661466
clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
1467+
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
14671468
mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
14681469
<CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
14691470
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;

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