@@ -2746,6 +2746,36 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
27462746 adev -> ip_versions [UVD_HWIP ][1 ] = IP_VERSION (2 , 6 , 0 );
27472747 adev -> ip_versions [XGMI_HWIP ][0 ] = IP_VERSION (6 , 1 , 0 );
27482748 break ;
2749+ case CHIP_CYAN_SKILLFISH :
2750+ if (adev -> apu_flags & AMD_APU_IS_CYAN_SKILLFISH2 ) {
2751+ r = amdgpu_discovery_reg_base_init (adev );
2752+ if (r )
2753+ return - EINVAL ;
2754+
2755+ amdgpu_discovery_harvest_ip (adev );
2756+ amdgpu_discovery_get_gfx_info (adev );
2757+ amdgpu_discovery_get_mall_info (adev );
2758+ amdgpu_discovery_get_vcn_info (adev );
2759+ } else {
2760+ cyan_skillfish_reg_base_init (adev );
2761+ adev -> sdma .num_instances = 2 ;
2762+ adev -> ip_versions [MMHUB_HWIP ][0 ] = IP_VERSION (2 , 0 , 3 );
2763+ adev -> ip_versions [ATHUB_HWIP ][0 ] = IP_VERSION (2 , 0 , 3 );
2764+ adev -> ip_versions [OSSSYS_HWIP ][0 ] = IP_VERSION (5 , 0 , 1 );
2765+ adev -> ip_versions [HDP_HWIP ][0 ] = IP_VERSION (5 , 0 , 1 );
2766+ adev -> ip_versions [SDMA0_HWIP ][0 ] = IP_VERSION (5 , 0 , 1 );
2767+ adev -> ip_versions [SDMA1_HWIP ][1 ] = IP_VERSION (5 , 0 , 1 );
2768+ adev -> ip_versions [DF_HWIP ][0 ] = IP_VERSION (3 , 5 , 0 );
2769+ adev -> ip_versions [NBIO_HWIP ][0 ] = IP_VERSION (2 , 1 , 1 );
2770+ adev -> ip_versions [UMC_HWIP ][0 ] = IP_VERSION (8 , 1 , 1 );
2771+ adev -> ip_versions [MP0_HWIP ][0 ] = IP_VERSION (11 , 0 , 8 );
2772+ adev -> ip_versions [MP1_HWIP ][0 ] = IP_VERSION (11 , 0 , 8 );
2773+ adev -> ip_versions [THM_HWIP ][0 ] = IP_VERSION (11 , 0 , 1 );
2774+ adev -> ip_versions [SMUIO_HWIP ][0 ] = IP_VERSION (11 , 0 , 8 );
2775+ adev -> ip_versions [GC_HWIP ][0 ] = IP_VERSION (10 , 1 , 3 );
2776+ adev -> ip_versions [UVD_HWIP ][0 ] = IP_VERSION (2 , 0 , 3 );
2777+ }
2778+ break ;
27492779 default :
27502780 r = amdgpu_discovery_reg_base_init (adev );
27512781 if (r ) {
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