@@ -2610,8 +2610,8 @@ static unsigned long rt5682s_wclk_recalc_rate(struct clk_hw *hw,
26102610 return rt5682s -> lrck [RT5682S_AIF1 ];
26112611}
26122612
2613- static long rt5682s_wclk_round_rate (struct clk_hw * hw , unsigned long rate ,
2614- unsigned long * parent_rate )
2613+ static int rt5682s_wclk_determine_rate (struct clk_hw * hw ,
2614+ struct clk_rate_request * req )
26152615{
26162616 struct rt5682s_priv * rt5682s =
26172617 container_of (hw , struct rt5682s_priv , dai_clks_hw [RT5682S_DAI_WCLK_IDX ]);
@@ -2624,13 +2624,13 @@ static long rt5682s_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
26242624 * Only accept to set wclk rate to 44.1k or 48kHz.
26252625 * It will force to 48kHz if not both.
26262626 */
2627- if (rate != CLK_48 && rate != CLK_44 ) {
2627+ if (req -> rate != CLK_48 && req -> rate != CLK_44 ) {
26282628 dev_warn (component -> dev , "%s: clk %s only support %d or %d Hz output\n" ,
26292629 __func__ , clk_name , CLK_44 , CLK_48 );
2630- rate = CLK_48 ;
2630+ req -> rate = CLK_48 ;
26312631 }
26322632
2633- return rate ;
2633+ return 0 ;
26342634}
26352635
26362636static int rt5682s_wclk_set_rate (struct clk_hw * hw , unsigned long rate ,
@@ -2719,14 +2719,14 @@ static unsigned long rt5682s_bclk_get_factor(unsigned long rate,
27192719 return 256 ;
27202720}
27212721
2722- static long rt5682s_bclk_round_rate (struct clk_hw * hw , unsigned long rate ,
2723- unsigned long * parent_rate )
2722+ static int rt5682s_bclk_determine_rate (struct clk_hw * hw ,
2723+ struct clk_rate_request * req )
27242724{
27252725 struct rt5682s_priv * rt5682s =
27262726 container_of (hw , struct rt5682s_priv , dai_clks_hw [RT5682S_DAI_BCLK_IDX ]);
27272727 unsigned long factor ;
27282728
2729- if (!* parent_rate || !rt5682s_clk_check (rt5682s ))
2729+ if (!req -> best_parent_rate || !rt5682s_clk_check (rt5682s ))
27302730 return - EINVAL ;
27312731
27322732 /*
@@ -2736,9 +2736,11 @@ static long rt5682s_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
27362736 * and find the appropriate multiplier of BCLK to
27372737 * get the rounded down BCLK value.
27382738 */
2739- factor = rt5682s_bclk_get_factor (rate , * parent_rate );
2739+ factor = rt5682s_bclk_get_factor (req -> rate , req -> best_parent_rate );
2740+
2741+ req -> rate = req -> best_parent_rate * factor ;
27402742
2741- return * parent_rate * factor ;
2743+ return 0 ;
27422744}
27432745
27442746static int rt5682s_bclk_set_rate (struct clk_hw * hw , unsigned long rate ,
@@ -2769,12 +2771,12 @@ static const struct clk_ops rt5682s_dai_clk_ops[RT5682S_DAI_NUM_CLKS] = {
27692771 .prepare = rt5682s_wclk_prepare ,
27702772 .unprepare = rt5682s_wclk_unprepare ,
27712773 .recalc_rate = rt5682s_wclk_recalc_rate ,
2772- .round_rate = rt5682s_wclk_round_rate ,
2774+ .determine_rate = rt5682s_wclk_determine_rate ,
27732775 .set_rate = rt5682s_wclk_set_rate ,
27742776 },
27752777 [RT5682S_DAI_BCLK_IDX ] = {
27762778 .recalc_rate = rt5682s_bclk_recalc_rate ,
2777- .round_rate = rt5682s_bclk_round_rate ,
2779+ .determine_rate = rt5682s_bclk_determine_rate ,
27782780 .set_rate = rt5682s_bclk_set_rate ,
27792781 },
27802782};
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