1616
1717enum trap_behaviour {
1818 BEHAVE_HANDLE_LOCALLY = 0 ,
19+
1920 BEHAVE_FORWARD_READ = BIT (0 ),
2021 BEHAVE_FORWARD_WRITE = BIT (1 ),
21- BEHAVE_FORWARD_ANY = BEHAVE_FORWARD_READ | BEHAVE_FORWARD_WRITE ,
22+ BEHAVE_FORWARD_RW = BEHAVE_FORWARD_READ | BEHAVE_FORWARD_WRITE ,
2223};
2324
2425struct trap_bits {
@@ -138,7 +139,7 @@ static const struct trap_bits coarse_trap_bits[] = {
138139 .index = HCR_EL2 ,
139140 .value = HCR_TID2 ,
140141 .mask = HCR_TID2 ,
141- .behaviour = BEHAVE_FORWARD_ANY ,
142+ .behaviour = BEHAVE_FORWARD_RW ,
142143 },
143144 [CGT_HCR_TID3 ] = {
144145 .index = HCR_EL2 ,
@@ -162,37 +163,37 @@ static const struct trap_bits coarse_trap_bits[] = {
162163 .index = HCR_EL2 ,
163164 .value = HCR_TIDCP ,
164165 .mask = HCR_TIDCP ,
165- .behaviour = BEHAVE_FORWARD_ANY ,
166+ .behaviour = BEHAVE_FORWARD_RW ,
166167 },
167168 [CGT_HCR_TACR ] = {
168169 .index = HCR_EL2 ,
169170 .value = HCR_TACR ,
170171 .mask = HCR_TACR ,
171- .behaviour = BEHAVE_FORWARD_ANY ,
172+ .behaviour = BEHAVE_FORWARD_RW ,
172173 },
173174 [CGT_HCR_TSW ] = {
174175 .index = HCR_EL2 ,
175176 .value = HCR_TSW ,
176177 .mask = HCR_TSW ,
177- .behaviour = BEHAVE_FORWARD_ANY ,
178+ .behaviour = BEHAVE_FORWARD_RW ,
178179 },
179180 [CGT_HCR_TPC ] = { /* Also called TCPC when FEAT_DPB is implemented */
180181 .index = HCR_EL2 ,
181182 .value = HCR_TPC ,
182183 .mask = HCR_TPC ,
183- .behaviour = BEHAVE_FORWARD_ANY ,
184+ .behaviour = BEHAVE_FORWARD_RW ,
184185 },
185186 [CGT_HCR_TPU ] = {
186187 .index = HCR_EL2 ,
187188 .value = HCR_TPU ,
188189 .mask = HCR_TPU ,
189- .behaviour = BEHAVE_FORWARD_ANY ,
190+ .behaviour = BEHAVE_FORWARD_RW ,
190191 },
191192 [CGT_HCR_TTLB ] = {
192193 .index = HCR_EL2 ,
193194 .value = HCR_TTLB ,
194195 .mask = HCR_TTLB ,
195- .behaviour = BEHAVE_FORWARD_ANY ,
196+ .behaviour = BEHAVE_FORWARD_RW ,
196197 },
197198 [CGT_HCR_TVM ] = {
198199 .index = HCR_EL2 ,
@@ -204,7 +205,7 @@ static const struct trap_bits coarse_trap_bits[] = {
204205 .index = HCR_EL2 ,
205206 .value = HCR_TDZ ,
206207 .mask = HCR_TDZ ,
207- .behaviour = BEHAVE_FORWARD_ANY ,
208+ .behaviour = BEHAVE_FORWARD_RW ,
208209 },
209210 [CGT_HCR_TRVM ] = {
210211 .index = HCR_EL2 ,
@@ -216,205 +217,205 @@ static const struct trap_bits coarse_trap_bits[] = {
216217 .index = HCR_EL2 ,
217218 .value = HCR_TLOR ,
218219 .mask = HCR_TLOR ,
219- .behaviour = BEHAVE_FORWARD_ANY ,
220+ .behaviour = BEHAVE_FORWARD_RW ,
220221 },
221222 [CGT_HCR_TERR ] = {
222223 .index = HCR_EL2 ,
223224 .value = HCR_TERR ,
224225 .mask = HCR_TERR ,
225- .behaviour = BEHAVE_FORWARD_ANY ,
226+ .behaviour = BEHAVE_FORWARD_RW ,
226227 },
227228 [CGT_HCR_APK ] = {
228229 .index = HCR_EL2 ,
229230 .value = 0 ,
230231 .mask = HCR_APK ,
231- .behaviour = BEHAVE_FORWARD_ANY ,
232+ .behaviour = BEHAVE_FORWARD_RW ,
232233 },
233234 [CGT_HCR_NV ] = {
234235 .index = HCR_EL2 ,
235236 .value = HCR_NV ,
236237 .mask = HCR_NV ,
237- .behaviour = BEHAVE_FORWARD_ANY ,
238+ .behaviour = BEHAVE_FORWARD_RW ,
238239 },
239240 [CGT_HCR_NV_nNV2 ] = {
240241 .index = HCR_EL2 ,
241242 .value = HCR_NV ,
242243 .mask = HCR_NV | HCR_NV2 ,
243- .behaviour = BEHAVE_FORWARD_ANY ,
244+ .behaviour = BEHAVE_FORWARD_RW ,
244245 },
245246 [CGT_HCR_NV1_nNV2 ] = {
246247 .index = HCR_EL2 ,
247248 .value = HCR_NV | HCR_NV1 ,
248249 .mask = HCR_NV | HCR_NV1 | HCR_NV2 ,
249- .behaviour = BEHAVE_FORWARD_ANY ,
250+ .behaviour = BEHAVE_FORWARD_RW ,
250251 },
251252 [CGT_HCR_AT ] = {
252253 .index = HCR_EL2 ,
253254 .value = HCR_AT ,
254255 .mask = HCR_AT ,
255- .behaviour = BEHAVE_FORWARD_ANY ,
256+ .behaviour = BEHAVE_FORWARD_RW ,
256257 },
257258 [CGT_HCR_nFIEN ] = {
258259 .index = HCR_EL2 ,
259260 .value = 0 ,
260261 .mask = HCR_FIEN ,
261- .behaviour = BEHAVE_FORWARD_ANY ,
262+ .behaviour = BEHAVE_FORWARD_RW ,
262263 },
263264 [CGT_HCR_TID4 ] = {
264265 .index = HCR_EL2 ,
265266 .value = HCR_TID4 ,
266267 .mask = HCR_TID4 ,
267- .behaviour = BEHAVE_FORWARD_ANY ,
268+ .behaviour = BEHAVE_FORWARD_RW ,
268269 },
269270 [CGT_HCR_TICAB ] = {
270271 .index = HCR_EL2 ,
271272 .value = HCR_TICAB ,
272273 .mask = HCR_TICAB ,
273- .behaviour = BEHAVE_FORWARD_ANY ,
274+ .behaviour = BEHAVE_FORWARD_RW ,
274275 },
275276 [CGT_HCR_TOCU ] = {
276277 .index = HCR_EL2 ,
277278 .value = HCR_TOCU ,
278279 .mask = HCR_TOCU ,
279- .behaviour = BEHAVE_FORWARD_ANY ,
280+ .behaviour = BEHAVE_FORWARD_RW ,
280281 },
281282 [CGT_HCR_ENSCXT ] = {
282283 .index = HCR_EL2 ,
283284 .value = 0 ,
284285 .mask = HCR_ENSCXT ,
285- .behaviour = BEHAVE_FORWARD_ANY ,
286+ .behaviour = BEHAVE_FORWARD_RW ,
286287 },
287288 [CGT_HCR_TTLBIS ] = {
288289 .index = HCR_EL2 ,
289290 .value = HCR_TTLBIS ,
290291 .mask = HCR_TTLBIS ,
291- .behaviour = BEHAVE_FORWARD_ANY ,
292+ .behaviour = BEHAVE_FORWARD_RW ,
292293 },
293294 [CGT_HCR_TTLBOS ] = {
294295 .index = HCR_EL2 ,
295296 .value = HCR_TTLBOS ,
296297 .mask = HCR_TTLBOS ,
297- .behaviour = BEHAVE_FORWARD_ANY ,
298+ .behaviour = BEHAVE_FORWARD_RW ,
298299 },
299300 [CGT_MDCR_TPMCR ] = {
300301 .index = MDCR_EL2 ,
301302 .value = MDCR_EL2_TPMCR ,
302303 .mask = MDCR_EL2_TPMCR ,
303- .behaviour = BEHAVE_FORWARD_ANY ,
304+ .behaviour = BEHAVE_FORWARD_RW ,
304305 },
305306 [CGT_MDCR_TPM ] = {
306307 .index = MDCR_EL2 ,
307308 .value = MDCR_EL2_TPM ,
308309 .mask = MDCR_EL2_TPM ,
309- .behaviour = BEHAVE_FORWARD_ANY ,
310+ .behaviour = BEHAVE_FORWARD_RW ,
310311 },
311312 [CGT_MDCR_TDE ] = {
312313 .index = MDCR_EL2 ,
313314 .value = MDCR_EL2_TDE ,
314315 .mask = MDCR_EL2_TDE ,
315- .behaviour = BEHAVE_FORWARD_ANY ,
316+ .behaviour = BEHAVE_FORWARD_RW ,
316317 },
317318 [CGT_MDCR_TDA ] = {
318319 .index = MDCR_EL2 ,
319320 .value = MDCR_EL2_TDA ,
320321 .mask = MDCR_EL2_TDA ,
321- .behaviour = BEHAVE_FORWARD_ANY ,
322+ .behaviour = BEHAVE_FORWARD_RW ,
322323 },
323324 [CGT_MDCR_TDOSA ] = {
324325 .index = MDCR_EL2 ,
325326 .value = MDCR_EL2_TDOSA ,
326327 .mask = MDCR_EL2_TDOSA ,
327- .behaviour = BEHAVE_FORWARD_ANY ,
328+ .behaviour = BEHAVE_FORWARD_RW ,
328329 },
329330 [CGT_MDCR_TDRA ] = {
330331 .index = MDCR_EL2 ,
331332 .value = MDCR_EL2_TDRA ,
332333 .mask = MDCR_EL2_TDRA ,
333- .behaviour = BEHAVE_FORWARD_ANY ,
334+ .behaviour = BEHAVE_FORWARD_RW ,
334335 },
335336 [CGT_MDCR_E2PB ] = {
336337 .index = MDCR_EL2 ,
337338 .value = 0 ,
338339 .mask = BIT (MDCR_EL2_E2PB_SHIFT ),
339- .behaviour = BEHAVE_FORWARD_ANY ,
340+ .behaviour = BEHAVE_FORWARD_RW ,
340341 },
341342 [CGT_MDCR_TPMS ] = {
342343 .index = MDCR_EL2 ,
343344 .value = MDCR_EL2_TPMS ,
344345 .mask = MDCR_EL2_TPMS ,
345- .behaviour = BEHAVE_FORWARD_ANY ,
346+ .behaviour = BEHAVE_FORWARD_RW ,
346347 },
347348 [CGT_MDCR_TTRF ] = {
348349 .index = MDCR_EL2 ,
349350 .value = MDCR_EL2_TTRF ,
350351 .mask = MDCR_EL2_TTRF ,
351- .behaviour = BEHAVE_FORWARD_ANY ,
352+ .behaviour = BEHAVE_FORWARD_RW ,
352353 },
353354 [CGT_MDCR_E2TB ] = {
354355 .index = MDCR_EL2 ,
355356 .value = 0 ,
356357 .mask = BIT (MDCR_EL2_E2TB_SHIFT ),
357- .behaviour = BEHAVE_FORWARD_ANY ,
358+ .behaviour = BEHAVE_FORWARD_RW ,
358359 },
359360 [CGT_MDCR_TDCC ] = {
360361 .index = MDCR_EL2 ,
361362 .value = MDCR_EL2_TDCC ,
362363 .mask = MDCR_EL2_TDCC ,
363- .behaviour = BEHAVE_FORWARD_ANY ,
364+ .behaviour = BEHAVE_FORWARD_RW ,
364365 },
365366 [CGT_CPACR_E0POE ] = {
366367 .index = CPTR_EL2 ,
367368 .value = CPACR_ELx_E0POE ,
368369 .mask = CPACR_ELx_E0POE ,
369- .behaviour = BEHAVE_FORWARD_ANY ,
370+ .behaviour = BEHAVE_FORWARD_RW ,
370371 },
371372 [CGT_CPTR_TAM ] = {
372373 .index = CPTR_EL2 ,
373374 .value = CPTR_EL2_TAM ,
374375 .mask = CPTR_EL2_TAM ,
375- .behaviour = BEHAVE_FORWARD_ANY ,
376+ .behaviour = BEHAVE_FORWARD_RW ,
376377 },
377378 [CGT_CPTR_TCPAC ] = {
378379 .index = CPTR_EL2 ,
379380 .value = CPTR_EL2_TCPAC ,
380381 .mask = CPTR_EL2_TCPAC ,
381- .behaviour = BEHAVE_FORWARD_ANY ,
382+ .behaviour = BEHAVE_FORWARD_RW ,
382383 },
383384 [CGT_HCRX_EnFPM ] = {
384385 .index = HCRX_EL2 ,
385386 .value = 0 ,
386387 .mask = HCRX_EL2_EnFPM ,
387- .behaviour = BEHAVE_FORWARD_ANY ,
388+ .behaviour = BEHAVE_FORWARD_RW ,
388389 },
389390 [CGT_HCRX_TCR2En ] = {
390391 .index = HCRX_EL2 ,
391392 .value = 0 ,
392393 .mask = HCRX_EL2_TCR2En ,
393- .behaviour = BEHAVE_FORWARD_ANY ,
394+ .behaviour = BEHAVE_FORWARD_RW ,
394395 },
395396 [CGT_ICH_HCR_TC ] = {
396397 .index = ICH_HCR_EL2 ,
397398 .value = ICH_HCR_TC ,
398399 .mask = ICH_HCR_TC ,
399- .behaviour = BEHAVE_FORWARD_ANY ,
400+ .behaviour = BEHAVE_FORWARD_RW ,
400401 },
401402 [CGT_ICH_HCR_TALL0 ] = {
402403 .index = ICH_HCR_EL2 ,
403404 .value = ICH_HCR_TALL0 ,
404405 .mask = ICH_HCR_TALL0 ,
405- .behaviour = BEHAVE_FORWARD_ANY ,
406+ .behaviour = BEHAVE_FORWARD_RW ,
406407 },
407408 [CGT_ICH_HCR_TALL1 ] = {
408409 .index = ICH_HCR_EL2 ,
409410 .value = ICH_HCR_TALL1 ,
410411 .mask = ICH_HCR_TALL1 ,
411- .behaviour = BEHAVE_FORWARD_ANY ,
412+ .behaviour = BEHAVE_FORWARD_RW ,
412413 },
413414 [CGT_ICH_HCR_TDIR ] = {
414415 .index = ICH_HCR_EL2 ,
415416 .value = ICH_HCR_TDIR ,
416417 .mask = ICH_HCR_TDIR ,
417- .behaviour = BEHAVE_FORWARD_ANY ,
418+ .behaviour = BEHAVE_FORWARD_RW ,
418419 },
419420};
420421
@@ -474,15 +475,15 @@ static enum trap_behaviour check_cnthctl_el1pcten(struct kvm_vcpu *vcpu)
474475 if (get_sanitized_cnthctl (vcpu ) & (CNTHCTL_EL1PCTEN << 10 ))
475476 return BEHAVE_HANDLE_LOCALLY ;
476477
477- return BEHAVE_FORWARD_ANY ;
478+ return BEHAVE_FORWARD_RW ;
478479}
479480
480481static enum trap_behaviour check_cnthctl_el1pten (struct kvm_vcpu * vcpu )
481482{
482483 if (get_sanitized_cnthctl (vcpu ) & (CNTHCTL_EL1PCEN << 10 ))
483484 return BEHAVE_HANDLE_LOCALLY ;
484485
485- return BEHAVE_FORWARD_ANY ;
486+ return BEHAVE_FORWARD_RW ;
486487}
487488
488489static enum trap_behaviour check_cptr_tta (struct kvm_vcpu * vcpu )
@@ -493,7 +494,7 @@ static enum trap_behaviour check_cptr_tta(struct kvm_vcpu *vcpu)
493494 val = translate_cptr_el2_to_cpacr_el1 (val );
494495
495496 if (val & CPACR_ELx_TTA )
496- return BEHAVE_FORWARD_ANY ;
497+ return BEHAVE_FORWARD_RW ;
497498
498499 return BEHAVE_HANDLE_LOCALLY ;
499500}
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