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net: dsa: mv88e6xx: fix supported_interfaces setup in mv88e6250_phylink_get_caps()
With the recent PHYLINK changes requiring supported_interfaces to be set, MV88E6250 family switches like the 88E6020 fail to probe - cmode is never initialized on these devices, so mv88e6250_phylink_get_caps() does not set any supported_interfaces flags. Instead of a cmode, on 88E6250 we have a read-only port mode value that encodes similar information. There is no reason to bother mapping port mode to the cmodes of other switch models; instead we introduce a mv88e6250_setup_supported_interfaces() that is called directly from mv88e6250_phylink_get_caps(). Fixes: de5c9bf ("net: phylink: require supported_interfaces to be filled") Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Link: https://lore.kernel.org/r/20240417103737.166651-1-matthias.schiffer@ew.tq-group.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
1 parent 9e91bf7 commit a4e3899

2 files changed

Lines changed: 71 additions & 8 deletions

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‎drivers/net/dsa/mv88e6xxx/chip.c‎

Lines changed: 52 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -566,13 +566,61 @@ static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
566566
phy_interface_set_rgmii(supported);
567567
}
568568

569-
static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
570-
struct phylink_config *config)
569+
static void
570+
mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port,
571+
struct phylink_config *config)
571572
{
572573
unsigned long *supported = config->supported_interfaces;
574+
int err;
575+
u16 reg;
573576

574-
/* Translate the default cmode */
575-
mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
577+
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
578+
if (err) {
579+
dev_err(chip->dev, "p%d: failed to read port status\n", port);
580+
return;
581+
}
582+
583+
switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {
584+
case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY:
585+
case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY:
586+
case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY:
587+
case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY:
588+
__set_bit(PHY_INTERFACE_MODE_REVMII, supported);
589+
break;
590+
591+
case MV88E6250_PORT_STS_PORTMODE_MII_HALF:
592+
case MV88E6250_PORT_STS_PORTMODE_MII_FULL:
593+
__set_bit(PHY_INTERFACE_MODE_MII, supported);
594+
break;
595+
596+
case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY:
597+
case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY:
598+
case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY:
599+
case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY:
600+
__set_bit(PHY_INTERFACE_MODE_REVRMII, supported);
601+
break;
602+
603+
case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL:
604+
case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL:
605+
__set_bit(PHY_INTERFACE_MODE_RMII, supported);
606+
break;
607+
608+
case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII:
609+
__set_bit(PHY_INTERFACE_MODE_RGMII, supported);
610+
break;
611+
612+
default:
613+
dev_err(chip->dev,
614+
"p%d: invalid port mode in status register: %04x\n",
615+
port, reg);
616+
}
617+
}
618+
619+
static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
620+
struct phylink_config *config)
621+
{
622+
if (!mv88e6xxx_phy_is_internal(chip, port))
623+
mv88e6250_setup_supported_interfaces(chip, port, config);
576624

577625
config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
578626
}

‎drivers/net/dsa/mv88e6xxx/port.h‎

Lines changed: 19 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -25,10 +25,25 @@
2525
#define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
2626
#define MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL 0x0a00
2727
#define MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL 0x0b00
28-
#define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF 0x0c00
29-
#define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF 0x0d00
30-
#define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL 0x0e00
31-
#define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL 0x0f00
28+
/* - Modes with PHY suffix use output instead of input clock
29+
* - Modes without RMII or RGMII use MII
30+
* - Modes without speed do not have a fixed speed specified in the manual
31+
* ("DC to x MHz" - variable clock support?)
32+
*/
33+
#define MV88E6250_PORT_STS_PORTMODE_MII_DISABLED 0x0000
34+
#define MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII 0x0100
35+
#define MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY 0x0200
36+
#define MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY 0x0400
37+
#define MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL 0x0600
38+
#define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL 0x0700
39+
#define MV88E6250_PORT_STS_PORTMODE_MII_HALF 0x0800
40+
#define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY 0x0900
41+
#define MV88E6250_PORT_STS_PORTMODE_MII_FULL 0x0a00
42+
#define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY 0x0b00
43+
#define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY 0x0c00
44+
#define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY 0x0d00
45+
#define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY 0x0e00
46+
#define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY 0x0f00
3247
#define MV88E6XXX_PORT_STS_LINK 0x0800
3348
#define MV88E6XXX_PORT_STS_DUPLEX 0x0400
3449
#define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300

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