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vsyrjalavsyrjala
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drm/i915: Plumb 'dsb' all way to the color commit hooks
Pass the 'dsb' all the way down to the color commit hooks so that we'll be able to update the double buffered color management registers (eg. CSC) via the DSB. Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240930170415.23841-13-ville.syrjala@linux.intel.com
1 parent 0138984 commit a6d4d97

4 files changed

Lines changed: 115 additions & 88 deletions

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‎drivers/gpu/drm/i915/display/intel_color.c‎

Lines changed: 106 additions & 82 deletions
Original file line numberDiff line numberDiff line change
@@ -39,15 +39,17 @@ struct intel_color_funcs {
3939
* the next vblank start, alongside any other double buffered
4040
* registers involved with the same commit. This hook is optional.
4141
*/
42-
void (*color_commit_noarm)(const struct intel_crtc_state *crtc_state);
42+
void (*color_commit_noarm)(struct intel_dsb *dsb,
43+
const struct intel_crtc_state *crtc_state);
4344
/*
4445
* Program arming double buffered color management registers
4546
* during vblank evasion. The registers (and whatever other registers
4647
* they arm that were written by color_commit_noarm) should then latch
4748
* during the next vblank start, alongside any other double buffered
4849
* registers involved with the same commit.
4950
*/
50-
void (*color_commit_arm)(const struct intel_crtc_state *crtc_state);
51+
void (*color_commit_arm)(struct intel_dsb *dsb,
52+
const struct intel_crtc_state *crtc_state);
5153
/*
5254
* Perform any extra tasks needed after all the
5355
* double buffered registers have been latched.
@@ -205,37 +207,44 @@ static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
205207
return result;
206208
}
207209

208-
static void ilk_update_pipe_csc(struct intel_crtc *crtc,
210+
static void ilk_update_pipe_csc(struct intel_dsb *dsb,
211+
struct intel_crtc *crtc,
209212
const struct intel_csc_matrix *csc)
210213
{
211-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
214+
struct intel_display *display = to_intel_display(crtc->base.dev);
212215
enum pipe pipe = crtc->pipe;
213216

214-
intel_de_write_fw(i915, PIPE_CSC_PREOFF_HI(pipe), csc->preoff[0]);
215-
intel_de_write_fw(i915, PIPE_CSC_PREOFF_ME(pipe), csc->preoff[1]);
216-
intel_de_write_fw(i915, PIPE_CSC_PREOFF_LO(pipe), csc->preoff[2]);
217-
218-
intel_de_write_fw(i915, PIPE_CSC_COEFF_RY_GY(pipe),
219-
csc->coeff[0] << 16 | csc->coeff[1]);
220-
intel_de_write_fw(i915, PIPE_CSC_COEFF_BY(pipe),
221-
csc->coeff[2] << 16);
222-
223-
intel_de_write_fw(i915, PIPE_CSC_COEFF_RU_GU(pipe),
224-
csc->coeff[3] << 16 | csc->coeff[4]);
225-
intel_de_write_fw(i915, PIPE_CSC_COEFF_BU(pipe),
226-
csc->coeff[5] << 16);
227-
228-
intel_de_write_fw(i915, PIPE_CSC_COEFF_RV_GV(pipe),
229-
csc->coeff[6] << 16 | csc->coeff[7]);
230-
intel_de_write_fw(i915, PIPE_CSC_COEFF_BV(pipe),
231-
csc->coeff[8] << 16);
232-
233-
if (DISPLAY_VER(i915) < 7)
217+
intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_HI(pipe),
218+
csc->preoff[0]);
219+
intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_ME(pipe),
220+
csc->preoff[1]);
221+
intel_de_write_dsb(display, dsb, PIPE_CSC_PREOFF_LO(pipe),
222+
csc->preoff[2]);
223+
224+
intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RY_GY(pipe),
225+
csc->coeff[0] << 16 | csc->coeff[1]);
226+
intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BY(pipe),
227+
csc->coeff[2] << 16);
228+
229+
intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RU_GU(pipe),
230+
csc->coeff[3] << 16 | csc->coeff[4]);
231+
intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BU(pipe),
232+
csc->coeff[5] << 16);
233+
234+
intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_RV_GV(pipe),
235+
csc->coeff[6] << 16 | csc->coeff[7]);
236+
intel_de_write_dsb(display, dsb, PIPE_CSC_COEFF_BV(pipe),
237+
csc->coeff[8] << 16);
238+
239+
if (DISPLAY_VER(display) < 7)
234240
return;
235241

236-
intel_de_write_fw(i915, PIPE_CSC_POSTOFF_HI(pipe), csc->postoff[0]);
237-
intel_de_write_fw(i915, PIPE_CSC_POSTOFF_ME(pipe), csc->postoff[1]);
238-
intel_de_write_fw(i915, PIPE_CSC_POSTOFF_LO(pipe), csc->postoff[2]);
242+
intel_de_write_dsb(display, dsb, PIPE_CSC_POSTOFF_HI(pipe),
243+
csc->postoff[0]);
244+
intel_de_write_dsb(display, dsb, PIPE_CSC_POSTOFF_ME(pipe),
245+
csc->postoff[1]);
246+
intel_de_write_dsb(display, dsb, PIPE_CSC_POSTOFF_LO(pipe),
247+
csc->postoff[2]);
239248
}
240249

241250
static void ilk_read_pipe_csc(struct intel_crtc *crtc,
@@ -304,34 +313,41 @@ static void skl_read_csc(struct intel_crtc_state *crtc_state)
304313
ilk_read_pipe_csc(crtc, &crtc_state->csc);
305314
}
306315

307-
static void icl_update_output_csc(struct intel_crtc *crtc,
316+
static void icl_update_output_csc(struct intel_dsb *dsb,
317+
struct intel_crtc *crtc,
308318
const struct intel_csc_matrix *csc)
309319
{
310-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
320+
struct intel_display *display = to_intel_display(crtc->base.dev);
311321
enum pipe pipe = crtc->pipe;
312322

313-
intel_de_write_fw(i915, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), csc->preoff[0]);
314-
intel_de_write_fw(i915, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), csc->preoff[1]);
315-
intel_de_write_fw(i915, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), csc->preoff[2]);
323+
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_PREOFF_HI(pipe),
324+
csc->preoff[0]);
325+
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_PREOFF_ME(pipe),
326+
csc->preoff[1]);
327+
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_PREOFF_LO(pipe),
328+
csc->preoff[2]);
316329

317-
intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
318-
csc->coeff[0] << 16 | csc->coeff[1]);
319-
intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_BY(pipe),
320-
csc->coeff[2] << 16);
330+
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
331+
csc->coeff[0] << 16 | csc->coeff[1]);
332+
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_BY(pipe),
333+
csc->coeff[2] << 16);
321334

322-
intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
323-
csc->coeff[3] << 16 | csc->coeff[4]);
324-
intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_BU(pipe),
325-
csc->coeff[5] << 16);
335+
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
336+
csc->coeff[3] << 16 | csc->coeff[4]);
337+
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_BU(pipe),
338+
csc->coeff[5] << 16);
326339

327-
intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
328-
csc->coeff[6] << 16 | csc->coeff[7]);
329-
intel_de_write_fw(i915, PIPE_CSC_OUTPUT_COEFF_BV(pipe),
330-
csc->coeff[8] << 16);
340+
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
341+
csc->coeff[6] << 16 | csc->coeff[7]);
342+
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_COEFF_BV(pipe),
343+
csc->coeff[8] << 16);
331344

332-
intel_de_write_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), csc->postoff[0]);
333-
intel_de_write_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), csc->postoff[1]);
334-
intel_de_write_fw(i915, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), csc->postoff[2]);
345+
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe),
346+
csc->postoff[0]);
347+
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe),
348+
csc->postoff[1]);
349+
intel_de_write_dsb(display, dsb, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe),
350+
csc->postoff[2]);
335351
}
336352

337353
static void icl_read_output_csc(struct intel_crtc *crtc,
@@ -526,12 +542,13 @@ static void ilk_assign_csc(struct intel_crtc_state *crtc_state)
526542
}
527543
}
528544

529-
static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
545+
static void ilk_load_csc_matrix(struct intel_dsb *dsb,
546+
const struct intel_crtc_state *crtc_state)
530547
{
531548
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
532549

533550
if (crtc_state->csc_enable)
534-
ilk_update_pipe_csc(crtc, &crtc_state->csc);
551+
ilk_update_pipe_csc(dsb, crtc, &crtc_state->csc);
535552
}
536553

537554
static void icl_assign_csc(struct intel_crtc_state *crtc_state)
@@ -563,15 +580,16 @@ static void icl_assign_csc(struct intel_crtc_state *crtc_state)
563580
}
564581
}
565582

566-
static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
583+
static void icl_load_csc_matrix(struct intel_dsb *dsb,
584+
const struct intel_crtc_state *crtc_state)
567585
{
568586
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
569587

570588
if (crtc_state->csc_mode & ICL_CSC_ENABLE)
571-
ilk_update_pipe_csc(crtc, &crtc_state->csc);
589+
ilk_update_pipe_csc(dsb, crtc, &crtc_state->csc);
572590

573591
if (crtc_state->csc_mode & ICL_OUTPUT_CSC_ENABLE)
574-
icl_update_output_csc(crtc, &crtc_state->output_csc);
592+
icl_update_output_csc(dsb, crtc, &crtc_state->output_csc);
575593
}
576594

577595
static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int frac_bits)
@@ -953,7 +971,8 @@ static void ilk_lut_12p4_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
953971
REG_FIELD_GET(PREC_PALETTE_12P4_BLUE_LDW_MASK, ldw);
954972
}
955973

956-
static void icl_color_commit_noarm(const struct intel_crtc_state *crtc_state)
974+
static void icl_color_commit_noarm(struct intel_dsb *dsb,
975+
const struct intel_crtc_state *crtc_state)
957976
{
958977
/*
959978
* Despite Wa_1406463849, ICL no longer suffers from the SKL
@@ -963,10 +982,11 @@ static void icl_color_commit_noarm(const struct intel_crtc_state *crtc_state)
963982
*
964983
* On TGL+ all CSC arming issues have been properly fixed.
965984
*/
966-
icl_load_csc_matrix(crtc_state);
985+
icl_load_csc_matrix(dsb, crtc_state);
967986
}
968987

969-
static void skl_color_commit_noarm(const struct intel_crtc_state *crtc_state)
988+
static void skl_color_commit_noarm(struct intel_dsb *dsb,
989+
const struct intel_crtc_state *crtc_state)
970990
{
971991
/*
972992
* Possibly related to display WA #1184, SKL CSC loses the latched
@@ -979,21 +999,24 @@ static void skl_color_commit_noarm(const struct intel_crtc_state *crtc_state)
979999
* which is called after PSR exit.
9801000
*/
9811001
if (!crtc_state->has_psr)
982-
ilk_load_csc_matrix(crtc_state);
1002+
ilk_load_csc_matrix(dsb, crtc_state);
9831003
}
9841004

985-
static void ilk_color_commit_noarm(const struct intel_crtc_state *crtc_state)
1005+
static void ilk_color_commit_noarm(struct intel_dsb *dsb,
1006+
const struct intel_crtc_state *crtc_state)
9861007
{
987-
ilk_load_csc_matrix(crtc_state);
1008+
ilk_load_csc_matrix(dsb, crtc_state);
9881009
}
9891010

990-
static void i9xx_color_commit_arm(const struct intel_crtc_state *crtc_state)
1011+
static void i9xx_color_commit_arm(struct intel_dsb *dsb,
1012+
const struct intel_crtc_state *crtc_state)
9911013
{
9921014
/* update TRANSCONF GAMMA_MODE */
9931015
i9xx_set_pipeconf(crtc_state);
9941016
}
9951017

996-
static void ilk_color_commit_arm(const struct intel_crtc_state *crtc_state)
1018+
static void ilk_color_commit_arm(struct intel_dsb *dsb,
1019+
const struct intel_crtc_state *crtc_state)
9971020
{
9981021
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
9991022
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
@@ -1005,7 +1028,8 @@ static void ilk_color_commit_arm(const struct intel_crtc_state *crtc_state)
10051028
crtc_state->csc_mode);
10061029
}
10071030

1008-
static void hsw_color_commit_arm(const struct intel_crtc_state *crtc_state)
1031+
static void hsw_color_commit_arm(struct intel_dsb *dsb,
1032+
const struct intel_crtc_state *crtc_state)
10091033
{
10101034
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
10111035
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
@@ -1076,15 +1100,16 @@ static void skl_get_config(struct intel_crtc_state *crtc_state)
10761100
crtc_state->csc_enable = true;
10771101
}
10781102

1079-
static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
1103+
static void skl_color_commit_arm(struct intel_dsb *dsb,
1104+
const struct intel_crtc_state *crtc_state)
10801105
{
10811106
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1082-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1107+
struct intel_display *display = to_intel_display(crtc->base.dev);
10831108
enum pipe pipe = crtc->pipe;
10841109
u32 val = 0;
10851110

10861111
if (crtc_state->has_psr)
1087-
ilk_load_csc_matrix(crtc_state);
1112+
ilk_load_csc_matrix(dsb, crtc_state);
10881113

10891114
/*
10901115
* We don't (yet) allow userspace to control the pipe background color,
@@ -1095,32 +1120,29 @@ static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
10951120
val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
10961121
if (crtc_state->csc_enable)
10971122
val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
1098-
intel_de_write(i915, SKL_BOTTOM_COLOR(pipe), val);
1123+
intel_de_write_dsb(display, dsb, SKL_BOTTOM_COLOR(pipe), val);
10991124

1100-
intel_de_write(i915, GAMMA_MODE(crtc->pipe),
1101-
crtc_state->gamma_mode);
1125+
intel_de_write_dsb(display, dsb, GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
11021126

1103-
intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe),
1104-
crtc_state->csc_mode);
1127+
intel_de_write_dsb(display, dsb, PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
11051128
}
11061129

1107-
static void icl_color_commit_arm(const struct intel_crtc_state *crtc_state)
1130+
static void icl_color_commit_arm(struct intel_dsb *dsb,
1131+
const struct intel_crtc_state *crtc_state)
11081132
{
11091133
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1110-
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1134+
struct intel_display *display = to_intel_display(crtc->base.dev);
11111135
enum pipe pipe = crtc->pipe;
11121136

11131137
/*
11141138
* We don't (yet) allow userspace to control the pipe background color,
11151139
* so force it to black.
11161140
*/
1117-
intel_de_write(i915, SKL_BOTTOM_COLOR(pipe), 0);
1141+
intel_de_write_dsb(display, dsb, SKL_BOTTOM_COLOR(pipe), 0);
11181142

1119-
intel_de_write(i915, GAMMA_MODE(crtc->pipe),
1120-
crtc_state->gamma_mode);
1143+
intel_de_write_dsb(display, dsb, GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
11211144

1122-
intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe),
1123-
crtc_state->csc_mode);
1145+
intel_de_write_dsb(display, dsb, PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
11241146
}
11251147

11261148
static void icl_color_post_update(const struct intel_crtc_state *crtc_state)
@@ -1876,19 +1898,21 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
18761898
i915->display.funcs.color->load_luts(crtc_state);
18771899
}
18781900

1879-
void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state)
1901+
void intel_color_commit_noarm(struct intel_dsb *dsb,
1902+
const struct intel_crtc_state *crtc_state)
18801903
{
18811904
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
18821905

18831906
if (i915->display.funcs.color->color_commit_noarm)
1884-
i915->display.funcs.color->color_commit_noarm(crtc_state);
1907+
i915->display.funcs.color->color_commit_noarm(dsb, crtc_state);
18851908
}
18861909

1887-
void intel_color_commit_arm(const struct intel_crtc_state *crtc_state)
1910+
void intel_color_commit_arm(struct intel_dsb *dsb,
1911+
const struct intel_crtc_state *crtc_state)
18881912
{
18891913
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
18901914

1891-
i915->display.funcs.color->color_commit_arm(crtc_state);
1915+
i915->display.funcs.color->color_commit_arm(dsb, crtc_state);
18921916

18931917
if (crtc_state->dsb_color_commit)
18941918
intel_dsb_commit(crtc_state->dsb_color_commit, false);
@@ -1907,8 +1931,8 @@ void intel_color_modeset(const struct intel_crtc_state *crtc_state)
19071931
struct intel_display *display = to_intel_display(crtc_state);
19081932

19091933
intel_color_load_luts(crtc_state);
1910-
intel_color_commit_noarm(crtc_state);
1911-
intel_color_commit_arm(crtc_state);
1934+
intel_color_commit_noarm(NULL, crtc_state);
1935+
intel_color_commit_arm(NULL, crtc_state);
19121936

19131937
if (DISPLAY_VER(display) < 9) {
19141938
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

‎drivers/gpu/drm/i915/display/intel_color.h‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
struct intel_atomic_state;
1212
struct intel_crtc_state;
1313
struct intel_crtc;
14+
struct intel_dsb;
1415
struct drm_i915_private;
1516
struct drm_property_blob;
1617

@@ -24,8 +25,10 @@ void intel_color_prepare_commit(struct intel_atomic_state *state,
2425
void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state);
2526
bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state);
2627
void intel_color_wait_commit(const struct intel_crtc_state *crtc_state);
27-
void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state);
28-
void intel_color_commit_arm(const struct intel_crtc_state *crtc_state);
28+
void intel_color_commit_noarm(struct intel_dsb *dsb,
29+
const struct intel_crtc_state *crtc_state);
30+
void intel_color_commit_arm(struct intel_dsb *dsb,
31+
const struct intel_crtc_state *crtc_state);
2932
void intel_color_post_update(const struct intel_crtc_state *crtc_state);
3033
void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
3134
void intel_color_modeset(const struct intel_crtc_state *crtc_state);

‎drivers/gpu/drm/i915/display/intel_display.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7072,7 +7072,7 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
70727072
*/
70737073
if (!modeset) {
70747074
if (intel_crtc_needs_color_update(new_crtc_state))
7075-
intel_color_commit_arm(new_crtc_state);
7075+
intel_color_commit_arm(NULL, new_crtc_state);
70767076

70777077
if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
70787078
bdw_set_pipe_misc(NULL, new_crtc_state);
@@ -7173,7 +7173,7 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
71737173

71747174
if (!modeset &&
71757175
intel_crtc_needs_color_update(new_crtc_state))
7176-
intel_color_commit_noarm(new_crtc_state);
7176+
intel_color_commit_noarm(NULL, new_crtc_state);
71777177

71787178
intel_crtc_planes_update_noarm(NULL, state, crtc);
71797179
}

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