Skip to content

Commit ac5bb37

Browse files
cyyselfjannau
cyyself
authored and
jannau
committed
drivers/perf: apple_m1: add known PMU events
This patch adds known PMU events that can be found on /usr/share/kpep in macOS. The m1_pmu_events and m1_pmu_event_affinity are generated from the script [1], which consumes the plist file from Apple. And then added these events to m1_pmu_perf_map and m1_pmu_event_attrs with Apple's documentation [2]. Link: https://github.com/cyyself/m1-pmu-gen [1] Link: https://developer.apple.com/download/apple-silicon-cpu-optimization-guide/ [2] Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Hector Martin <marcan@marcan.st>
1 parent 2db7f4e commit ac5bb37

1 file changed

Lines changed: 105 additions & 73 deletions

File tree

‎drivers/perf/apple_m1_cpu_pmu.c‎

Lines changed: 105 additions & 73 deletions
Original file line numberDiff line numberDiff line change
@@ -47,46 +47,79 @@
4747
* implementations, we'll have to introduce per cpu-type tables.
4848
*/
4949
enum m1_pmu_events {
50-
M1_PMU_PERFCTR_UNKNOWN_01 = 0x01,
51-
M1_PMU_PERFCTR_CPU_CYCLES = 0x02,
52-
M1_PMU_PERFCTR_INSTRUCTIONS = 0x8c,
53-
M1_PMU_PERFCTR_UNKNOWN_8d = 0x8d,
54-
M1_PMU_PERFCTR_UNKNOWN_8e = 0x8e,
55-
M1_PMU_PERFCTR_UNKNOWN_8f = 0x8f,
56-
M1_PMU_PERFCTR_UNKNOWN_90 = 0x90,
57-
M1_PMU_PERFCTR_UNKNOWN_93 = 0x93,
58-
M1_PMU_PERFCTR_UNKNOWN_94 = 0x94,
59-
M1_PMU_PERFCTR_UNKNOWN_95 = 0x95,
60-
M1_PMU_PERFCTR_UNKNOWN_96 = 0x96,
61-
M1_PMU_PERFCTR_UNKNOWN_97 = 0x97,
62-
M1_PMU_PERFCTR_UNKNOWN_98 = 0x98,
63-
M1_PMU_PERFCTR_UNKNOWN_99 = 0x99,
64-
M1_PMU_PERFCTR_UNKNOWN_9a = 0x9a,
65-
M1_PMU_PERFCTR_UNKNOWN_9b = 0x9b,
66-
M1_PMU_PERFCTR_UNKNOWN_9c = 0x9c,
67-
M1_PMU_PERFCTR_UNKNOWN_9f = 0x9f,
68-
M1_PMU_PERFCTR_UNKNOWN_bf = 0xbf,
69-
M1_PMU_PERFCTR_UNKNOWN_c0 = 0xc0,
70-
M1_PMU_PERFCTR_UNKNOWN_c1 = 0xc1,
71-
M1_PMU_PERFCTR_UNKNOWN_c4 = 0xc4,
72-
M1_PMU_PERFCTR_UNKNOWN_c5 = 0xc5,
73-
M1_PMU_PERFCTR_UNKNOWN_c6 = 0xc6,
74-
M1_PMU_PERFCTR_UNKNOWN_c8 = 0xc8,
75-
M1_PMU_PERFCTR_UNKNOWN_ca = 0xca,
76-
M1_PMU_PERFCTR_UNKNOWN_cb = 0xcb,
77-
M1_PMU_PERFCTR_UNKNOWN_f5 = 0xf5,
78-
M1_PMU_PERFCTR_UNKNOWN_f6 = 0xf6,
79-
M1_PMU_PERFCTR_UNKNOWN_f7 = 0xf7,
80-
M1_PMU_PERFCTR_UNKNOWN_f8 = 0xf8,
81-
M1_PMU_PERFCTR_UNKNOWN_fd = 0xfd,
82-
M1_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT,
50+
M1_PMU_PERFCTR_RETIRE_UOP = 0x1,
51+
M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE = 0x2,
52+
M1_PMU_PERFCTR_L1I_TLB_FILL = 0x4,
53+
M1_PMU_PERFCTR_L1D_TLB_FILL = 0x5,
54+
M1_PMU_PERFCTR_MMU_TABLE_WALK_INSTRUCTION = 0x7,
55+
M1_PMU_PERFCTR_MMU_TABLE_WALK_DATA = 0x8,
56+
M1_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION = 0xa,
57+
M1_PMU_PERFCTR_L2_TLB_MISS_DATA = 0xb,
58+
M1_PMU_PERFCTR_MMU_VIRTUAL_MEMORY_FAULT_NONSPEC = 0xd,
59+
M1_PMU_PERFCTR_SCHEDULE_UOP = 0x52,
60+
M1_PMU_PERFCTR_INTERRUPT_PENDING = 0x6c,
61+
M1_PMU_PERFCTR_MAP_STALL_DISPATCH = 0x70,
62+
M1_PMU_PERFCTR_MAP_REWIND = 0x75,
63+
M1_PMU_PERFCTR_MAP_STALL = 0x76,
64+
M1_PMU_PERFCTR_MAP_INT_UOP = 0x7c,
65+
M1_PMU_PERFCTR_MAP_LDST_UOP = 0x7d,
66+
M1_PMU_PERFCTR_MAP_SIMD_UOP = 0x7e,
67+
M1_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC = 0x84,
68+
M1_PMU_PERFCTR_INST_ALL = 0x8c,
69+
M1_PMU_PERFCTR_INST_BRANCH = 0x8d,
70+
M1_PMU_PERFCTR_INST_BRANCH_CALL = 0x8e,
71+
M1_PMU_PERFCTR_INST_BRANCH_RET = 0x8f,
72+
M1_PMU_PERFCTR_INST_BRANCH_TAKEN = 0x90,
73+
M1_PMU_PERFCTR_INST_BRANCH_INDIR = 0x93,
74+
M1_PMU_PERFCTR_INST_BRANCH_COND = 0x94,
75+
M1_PMU_PERFCTR_INST_INT_LD = 0x95,
76+
M1_PMU_PERFCTR_INST_INT_ST = 0x96,
77+
M1_PMU_PERFCTR_INST_INT_ALU = 0x97,
78+
M1_PMU_PERFCTR_INST_SIMD_LD = 0x98,
79+
M1_PMU_PERFCTR_INST_SIMD_ST = 0x99,
80+
M1_PMU_PERFCTR_INST_SIMD_ALU = 0x9a,
81+
M1_PMU_PERFCTR_INST_LDST = 0x9b,
82+
M1_PMU_PERFCTR_INST_BARRIER = 0x9c,
83+
M1_PMU_PERFCTR_UNKNOWN_9f = 0x9f,
84+
M1_PMU_PERFCTR_L1D_TLB_ACCESS = 0xa0,
85+
M1_PMU_PERFCTR_L1D_TLB_MISS = 0xa1,
86+
M1_PMU_PERFCTR_L1D_CACHE_MISS_ST = 0xa2,
87+
M1_PMU_PERFCTR_L1D_CACHE_MISS_LD = 0xa3,
88+
M1_PMU_PERFCTR_LD_UNIT_UOP = 0xa6,
89+
M1_PMU_PERFCTR_ST_UNIT_UOP = 0xa7,
90+
M1_PMU_PERFCTR_L1D_CACHE_WRITEBACK = 0xa8,
91+
M1_PMU_PERFCTR_LDST_X64_UOP = 0xb1,
92+
M1_PMU_PERFCTR_LDST_XPG_UOP = 0xb2,
93+
M1_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC = 0xb3,
94+
M1_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL = 0xb4,
95+
M1_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC = 0xbf,
96+
M1_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC = 0xc0,
97+
M1_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC = 0xc1,
98+
M1_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC = 0xc4,
99+
M1_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC = 0xc5,
100+
M1_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC = 0xc6,
101+
M1_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC = 0xc8,
102+
M1_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC = 0xca,
103+
M1_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC = 0xcb,
104+
M1_PMU_PERFCTR_L1I_TLB_MISS_DEMAND = 0xd4,
105+
M1_PMU_PERFCTR_MAP_DISPATCH_BUBBLE = 0xd6,
106+
M1_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND = 0xdb,
107+
M1_PMU_PERFCTR_FETCH_RESTART = 0xde,
108+
M1_PMU_PERFCTR_ST_NT_UOP = 0xe5,
109+
M1_PMU_PERFCTR_LD_NT_UOP = 0xe6,
110+
M1_PMU_PERFCTR_UNKNOWN_f5 = 0xf5,
111+
M1_PMU_PERFCTR_UNKNOWN_f6 = 0xf6,
112+
M1_PMU_PERFCTR_UNKNOWN_f7 = 0xf7,
113+
M1_PMU_PERFCTR_UNKNOWN_f8 = 0xf8,
114+
M1_PMU_PERFCTR_UNKNOWN_fd = 0xfd,
115+
M1_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT,
83116

84117
/*
85118
* From this point onwards, these are not actual HW events,
86119
* but attributes that get stored in hw->config_base.
87120
*/
88-
M1_PMU_CFG_COUNT_USER = BIT(8),
89-
M1_PMU_CFG_COUNT_KERNEL = BIT(9),
121+
M1_PMU_CFG_COUNT_USER = BIT(8),
122+
M1_PMU_CFG_COUNT_KERNEL = BIT(9),
90123
};
91124

92125
/*
@@ -96,46 +129,45 @@ enum m1_pmu_events {
96129
* counters had strange affinities.
97130
*/
98131
static const u16 m1_pmu_event_affinity[M1_PMU_PERFCTR_LAST + 1] = {
99-
[0 ... M1_PMU_PERFCTR_LAST] = ANY_BUT_0_1,
100-
[M1_PMU_PERFCTR_UNKNOWN_01] = BIT(7),
101-
[M1_PMU_PERFCTR_CPU_CYCLES] = ANY_BUT_0_1 | BIT(0),
102-
[M1_PMU_PERFCTR_INSTRUCTIONS] = BIT(7) | BIT(1),
103-
[M1_PMU_PERFCTR_UNKNOWN_8d] = ONLY_5_6_7,
104-
[M1_PMU_PERFCTR_UNKNOWN_8e] = ONLY_5_6_7,
105-
[M1_PMU_PERFCTR_UNKNOWN_8f] = ONLY_5_6_7,
106-
[M1_PMU_PERFCTR_UNKNOWN_90] = ONLY_5_6_7,
107-
[M1_PMU_PERFCTR_UNKNOWN_93] = ONLY_5_6_7,
108-
[M1_PMU_PERFCTR_UNKNOWN_94] = ONLY_5_6_7,
109-
[M1_PMU_PERFCTR_UNKNOWN_95] = ONLY_5_6_7,
110-
[M1_PMU_PERFCTR_UNKNOWN_96] = ONLY_5_6_7,
111-
[M1_PMU_PERFCTR_UNKNOWN_97] = BIT(7),
112-
[M1_PMU_PERFCTR_UNKNOWN_98] = ONLY_5_6_7,
113-
[M1_PMU_PERFCTR_UNKNOWN_99] = ONLY_5_6_7,
114-
[M1_PMU_PERFCTR_UNKNOWN_9a] = BIT(7),
115-
[M1_PMU_PERFCTR_UNKNOWN_9b] = ONLY_5_6_7,
116-
[M1_PMU_PERFCTR_UNKNOWN_9c] = ONLY_5_6_7,
117-
[M1_PMU_PERFCTR_UNKNOWN_9f] = BIT(7),
118-
[M1_PMU_PERFCTR_UNKNOWN_bf] = ONLY_5_6_7,
119-
[M1_PMU_PERFCTR_UNKNOWN_c0] = ONLY_5_6_7,
120-
[M1_PMU_PERFCTR_UNKNOWN_c1] = ONLY_5_6_7,
121-
[M1_PMU_PERFCTR_UNKNOWN_c4] = ONLY_5_6_7,
122-
[M1_PMU_PERFCTR_UNKNOWN_c5] = ONLY_5_6_7,
123-
[M1_PMU_PERFCTR_UNKNOWN_c6] = ONLY_5_6_7,
124-
[M1_PMU_PERFCTR_UNKNOWN_c8] = ONLY_5_6_7,
125-
[M1_PMU_PERFCTR_UNKNOWN_ca] = ONLY_5_6_7,
126-
[M1_PMU_PERFCTR_UNKNOWN_cb] = ONLY_5_6_7,
127-
[M1_PMU_PERFCTR_UNKNOWN_f5] = ONLY_2_4_6,
128-
[M1_PMU_PERFCTR_UNKNOWN_f6] = ONLY_2_4_6,
129-
[M1_PMU_PERFCTR_UNKNOWN_f7] = ONLY_2_4_6,
130-
[M1_PMU_PERFCTR_UNKNOWN_f8] = ONLY_2_TO_7,
131-
[M1_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6,
132+
[0 ... M1_PMU_PERFCTR_LAST] = ANY_BUT_0_1,
133+
[M1_PMU_PERFCTR_RETIRE_UOP] = BIT(7),
134+
[M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE] = ANY_BUT_0_1 | BIT(0),
135+
[M1_PMU_PERFCTR_INST_ALL] = BIT(7) | BIT(1),
136+
[M1_PMU_PERFCTR_INST_BRANCH] = ONLY_5_6_7,
137+
[M1_PMU_PERFCTR_INST_BRANCH_CALL] = ONLY_5_6_7,
138+
[M1_PMU_PERFCTR_INST_BRANCH_RET] = ONLY_5_6_7,
139+
[M1_PMU_PERFCTR_INST_BRANCH_TAKEN] = ONLY_5_6_7,
140+
[M1_PMU_PERFCTR_INST_BRANCH_INDIR] = ONLY_5_6_7,
141+
[M1_PMU_PERFCTR_INST_BRANCH_COND] = ONLY_5_6_7,
142+
[M1_PMU_PERFCTR_INST_INT_LD] = ONLY_5_6_7,
143+
[M1_PMU_PERFCTR_INST_INT_ST] = BIT(7),
144+
[M1_PMU_PERFCTR_INST_INT_ALU] = BIT(7),
145+
[M1_PMU_PERFCTR_INST_SIMD_LD] = ONLY_5_6_7,
146+
[M1_PMU_PERFCTR_INST_SIMD_ST] = ONLY_5_6_7,
147+
[M1_PMU_PERFCTR_INST_SIMD_ALU] = BIT(7),
148+
[M1_PMU_PERFCTR_INST_LDST] = BIT(7),
149+
[M1_PMU_PERFCTR_INST_BARRIER] = ONLY_5_6_7,
150+
[M1_PMU_PERFCTR_UNKNOWN_9f] = BIT(7),
151+
[M1_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] = ONLY_5_6_7,
152+
[M1_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] = ONLY_5_6_7,
153+
[M1_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] = ONLY_5_6_7,
154+
[M1_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] = ONLY_5_6_7,
155+
[M1_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] = ONLY_5_6_7,
156+
[M1_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
157+
[M1_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
158+
[M1_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] = ONLY_5_6_7,
159+
[M1_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] = ONLY_5_6_7,
160+
[M1_PMU_PERFCTR_UNKNOWN_f5] = ONLY_2_4_6,
161+
[M1_PMU_PERFCTR_UNKNOWN_f6] = ONLY_2_4_6,
162+
[M1_PMU_PERFCTR_UNKNOWN_f7] = ONLY_2_4_6,
163+
[M1_PMU_PERFCTR_UNKNOWN_f8] = ONLY_2_TO_7,
164+
[M1_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6,
132165
};
133166

134167
static const unsigned m1_pmu_perf_map[PERF_COUNT_HW_MAX] = {
135168
PERF_MAP_ALL_UNSUPPORTED,
136-
[PERF_COUNT_HW_CPU_CYCLES] = M1_PMU_PERFCTR_CPU_CYCLES,
137-
[PERF_COUNT_HW_INSTRUCTIONS] = M1_PMU_PERFCTR_INSTRUCTIONS,
138-
/* No idea about the rest yet */
169+
[PERF_COUNT_HW_CPU_CYCLES] = M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE,
170+
[PERF_COUNT_HW_INSTRUCTIONS] = M1_PMU_PERFCTR_INST_ALL,
139171
};
140172

141173
/* sysfs definitions */
@@ -154,8 +186,8 @@ static ssize_t m1_pmu_events_sysfs_show(struct device *dev,
154186
PMU_EVENT_ATTR_ID(name, m1_pmu_events_sysfs_show, config)
155187

156188
static struct attribute *m1_pmu_event_attrs[] = {
157-
M1_PMU_EVENT_ATTR(cycles, M1_PMU_PERFCTR_CPU_CYCLES),
158-
M1_PMU_EVENT_ATTR(instructions, M1_PMU_PERFCTR_INSTRUCTIONS),
189+
M1_PMU_EVENT_ATTR(cycles, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE),
190+
M1_PMU_EVENT_ATTR(instructions, M1_PMU_PERFCTR_INST_ALL),
159191
NULL,
160192
};
161193

0 commit comments

Comments
 (0)