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Merge tag 'arm-soc/for-6.12/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
This pull request contains Broadcom ARM64 SoCs Device Tree changes for 6.12, please pull the following: - Andrea adds a minimal Device Tree for the Raspberry Pi 5 (2712) - Stefan adjusts the bcm2837/bcm2712 bcm2836-l1-intc node name to conform to the binding changes * tag 'arm-soc/for-6.12/devicetree-arm64' of https://github.com/Broadcom/stblinux: ARM: dts: bcm2837/bcm2712: adjust local intc node names arm64: dts: broadcom: Add minimal support for Raspberry Pi 5 Link: https://lore.kernel.org/r/20240906180643.2275460-2-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents d053652 + eb81f43 commit af0103e

4 files changed

Lines changed: 349 additions & 1 deletion

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‎arch/arm/boot/dts/broadcom/bcm2837.dtsi‎

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@@ -9,7 +9,7 @@
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<0x40000000 0x40000000 0x00001000>;
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dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
1111

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local_intc: local_intc@40000000 {
12+
local_intc: interrupt-controller@40000000 {
1313
compatible = "brcm,bcm2836-l1-intc";
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reg = <0x40000000 0x100>;
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interrupt-controller;

‎arch/arm64/boot/dts/broadcom/Makefile‎

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@@ -6,6 +6,7 @@ DTC_FLAGS := -@
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dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \
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bcm2711-rpi-4-b.dtb \
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bcm2711-rpi-cm4-io.dtb \
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bcm2712-rpi-5-b.dtb \
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bcm2837-rpi-3-a-plus.dtb \
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bcm2837-rpi-3-b.dtb \
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bcm2837-rpi-3-b-plus.dtb \

‎arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts‎

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "bcm2712.dtsi"
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/ {
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compatible = "raspberrypi,5-model-b", "brcm,bcm2712";
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model = "Raspberry Pi 5";
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aliases {
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serial10 = &uart10;
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};
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chosen: chosen {
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stdout-path = "serial10:115200n8";
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};
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/* Will be filled by the bootloader */
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memory@0 {
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device_type = "memory";
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reg = <0 0 0 0x28000000>;
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};
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sd_io_1v8_reg: sd-io-1v8-reg {
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compatible = "regulator-gpio";
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regulator-name = "vdd-sd-io";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-settling-time-us = <5000>;
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gpios = <&gio_aon 3 GPIO_ACTIVE_HIGH>;
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states = <1800000 1>,
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<3300000 0>;
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};
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sd_vcc_reg: sd-vcc-reg {
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compatible = "regulator-fixed";
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regulator-name = "vcc-sd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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enable-active-high;
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gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>;
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};
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};
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/* The Debug UART, on Rpi5 it's on JST-SH 1.0mm 3-pin connector
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* labeled "UART", i.e. the interface with the system console.
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*/
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&uart10 {
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status = "okay";
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};
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/* SDIO1 is used to drive the SD card */
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&sdio1 {
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vqmmc-supply = <&sd_io_1v8_reg>;
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vmmc-supply = <&sd_vcc_reg>;
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bus-width = <4>;
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sd-uhs-sdr50;
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sd-uhs-ddr50;
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sd-uhs-sdr104;
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};

‎arch/arm64/boot/dts/broadcom/bcm2712.dtsi‎

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "brcm,bcm2712";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gicv2>;
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clocks {
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/* The oscillator is the root of the clock tree. */
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clk_osc: clk-osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "osc";
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clock-frequency = <54000000>;
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};
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clk_vpu: clk-vpu {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <750000000>;
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clock-output-names = "vpu-clock";
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};
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clk_uart: clk-uart {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <9216000>;
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clock-output-names = "uart-clock";
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};
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clk_emmc2: clk-emmc2 {
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compatible = "fixed-clock";
37+
#clock-cells = <0>;
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clock-frequency = <200000000>;
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clock-output-names = "emmc2-clock";
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};
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};
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cpus: cpus {
44+
#address-cells = <1>;
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#size-cells = <0>;
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/* Source for L1 d/i cache-line-size, cache-sets, cache-size
48+
* https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en
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* Source for L2 cache-line-size and cache-sets:
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* https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en
51+
* and for cache-size:
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* https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
53+
*/
54+
cpu0: cpu@0 {
55+
device_type = "cpu";
56+
compatible = "arm,cortex-a76";
57+
reg = <0x000>;
58+
enable-method = "psci";
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d-cache-size = <0x10000>;
60+
d-cache-line-size = <64>;
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d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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i-cache-size = <0x10000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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next-level-cache = <&l2_cache_l0>;
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l2_cache_l0: l2-cache-l0 {
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compatible = "cache";
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cache-size = <0x80000>;
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cache-line-size = <128>;
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cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
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cache-level = <2>;
73+
cache-unified;
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next-level-cache = <&l3_cache>;
75+
};
76+
};
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78+
cpu1: cpu@1 {
79+
device_type = "cpu";
80+
compatible = "arm,cortex-a76";
81+
reg = <0x100>;
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enable-method = "psci";
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d-cache-size = <0x10000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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i-cache-size = <0x10000>;
87+
i-cache-line-size = <64>;
88+
i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
89+
next-level-cache = <&l2_cache_l1>;
90+
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l2_cache_l1: l2-cache-l1 {
92+
compatible = "cache";
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cache-size = <0x80000>;
94+
cache-line-size = <128>;
95+
cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
96+
cache-level = <2>;
97+
cache-unified;
98+
next-level-cache = <&l3_cache>;
99+
};
100+
};
101+
102+
cpu2: cpu@2 {
103+
device_type = "cpu";
104+
compatible = "arm,cortex-a76";
105+
reg = <0x200>;
106+
enable-method = "psci";
107+
d-cache-size = <0x10000>;
108+
d-cache-line-size = <64>;
109+
d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
110+
i-cache-size = <0x10000>;
111+
i-cache-line-size = <64>;
112+
i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
113+
next-level-cache = <&l2_cache_l2>;
114+
115+
l2_cache_l2: l2-cache-l2 {
116+
compatible = "cache";
117+
cache-size = <0x80000>;
118+
cache-line-size = <128>;
119+
cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
120+
cache-level = <2>;
121+
cache-unified;
122+
next-level-cache = <&l3_cache>;
123+
};
124+
};
125+
126+
cpu3: cpu@3 {
127+
device_type = "cpu";
128+
compatible = "arm,cortex-a76";
129+
reg = <0x300>;
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enable-method = "psci";
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d-cache-size = <0x10000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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i-cache-size = <0x10000>;
135+
i-cache-line-size = <64>;
136+
i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
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next-level-cache = <&l2_cache_l3>;
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139+
l2_cache_l3: l2-cache-l3 {
140+
compatible = "cache";
141+
cache-size = <0x80000>;
142+
cache-line-size = <128>;
143+
cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
144+
cache-level = <2>;
145+
cache-unified;
146+
next-level-cache = <&l3_cache>;
147+
};
148+
};
149+
150+
/* Source for cache-line-size and cache-sets:
151+
* https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en
152+
* Source for cache-size:
153+
* https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
154+
*/
155+
l3_cache: l3-cache {
156+
compatible = "cache";
157+
cache-size = <0x200000>;
158+
cache-line-size = <64>;
159+
cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set
160+
cache-level = <3>;
161+
cache-unified;
162+
};
163+
};
164+
165+
psci {
166+
method = "smc";
167+
compatible = "arm,psci-1.0", "arm,psci-0.2";
168+
};
169+
170+
rmem: reserved-memory {
171+
ranges;
172+
#address-cells = <2>;
173+
#size-cells = <2>;
174+
175+
atf@0 {
176+
reg = <0x0 0x0 0x0 0x80000>;
177+
no-map;
178+
};
179+
180+
cma: linux,cma {
181+
compatible = "shared-dma-pool";
182+
size = <0x0 0x4000000>; /* 64MB */
183+
reusable;
184+
linux,cma-default;
185+
alloc-ranges = <0x0 0x00000000 0x0 0x40000000>;
186+
};
187+
};
188+
189+
soc: soc@107c000000 {
190+
compatible = "simple-bus";
191+
ranges = <0x00000000 0x10 0x00000000 0x80000000>;
192+
#address-cells = <1>;
193+
#size-cells = <1>;
194+
195+
sdio1: mmc@fff000 {
196+
compatible = "brcm,bcm2712-sdhci",
197+
"brcm,sdhci-brcmstb";
198+
reg = <0x00fff000 0x260>,
199+
<0x00fff400 0x200>;
200+
reg-names = "host", "cfg";
201+
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>;
202+
clocks = <&clk_emmc2>;
203+
clock-names = "sw_sdio";
204+
mmc-ddr-3_3v;
205+
};
206+
207+
system_timer: timer@7c003000 {
208+
compatible = "brcm,bcm2835-system-timer";
209+
reg = <0x7c003000 0x1000>;
210+
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
211+
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
212+
<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
213+
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
214+
clock-frequency = <1000000>;
215+
};
216+
217+
mailbox: mailbox@7c013880 {
218+
compatible = "brcm,bcm2835-mbox";
219+
reg = <0x7c013880 0x40>;
220+
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
221+
#mbox-cells = <0>;
222+
};
223+
224+
local_intc: interrupt-controller@7cd00000 {
225+
compatible = "brcm,bcm2836-l1-intc";
226+
reg = <0x7cd00000 0x100>;
227+
};
228+
229+
uart10: serial@7d001000 {
230+
compatible = "arm,pl011", "arm,primecell";
231+
reg = <0x7d001000 0x200>;
232+
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
233+
clocks = <&clk_uart>, <&clk_vpu>;
234+
clock-names = "uartclk", "apb_pclk";
235+
arm,primecell-periphid = <0x00241011>;
236+
status = "disabled";
237+
};
238+
239+
interrupt-controller@7d517000 {
240+
compatible = "brcm,bcm7271-l2-intc";
241+
reg = <0x7d517000 0x10>;
242+
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
243+
interrupt-controller;
244+
#interrupt-cells = <1>;
245+
};
246+
247+
gio_aon: gpio@7d517c00 {
248+
compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
249+
reg = <0x7d517c00 0x40>;
250+
gpio-controller;
251+
#gpio-cells = <2>;
252+
brcm,gpio-bank-widths = <17 6>;
253+
/* The lack of 'interrupt-controller' property here is intended:
254+
* don't use GIO_AON as an interrupt controller because it will
255+
* clash with the firmware monitoring the PMIC interrupt via the VPU.
256+
*/
257+
};
258+
259+
gicv2: interrupt-controller@7fff9000 {
260+
compatible = "arm,gic-400";
261+
reg = <0x7fff9000 0x1000>,
262+
<0x7fffa000 0x2000>,
263+
<0x7fffc000 0x2000>,
264+
<0x7fffe000 0x2000>;
265+
interrupt-controller;
266+
#interrupt-cells = <3>;
267+
};
268+
};
269+
270+
timer {
271+
compatible = "arm,armv8-timer";
272+
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
273+
IRQ_TYPE_LEVEL_LOW)>,
274+
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
275+
IRQ_TYPE_LEVEL_LOW)>,
276+
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
277+
IRQ_TYPE_LEVEL_LOW)>,
278+
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
279+
IRQ_TYPE_LEVEL_LOW)>,
280+
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) |
281+
IRQ_TYPE_LEVEL_LOW)>;
282+
};
283+
};

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