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spi-cadence: support transmission with
Merge series from Jun Guo <jun.guo@cixtech.com>: The Cadence SPI IP supports configurable FIFO data widths during integration. On some SoCs, the FIFO data width is designed to be 16 or 32 bits at the chip design stage. However, the current driver only supports communication with an 8-bit FIFO data width. Therefore, these patches are added to enable the driver to support communication with 16-bit and 32-bit FIFO data widths.
2 parents 1d562ba + 4e00135 commit af33092

245 files changed

Lines changed: 2139 additions & 937 deletions

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‎Documentation/devicetree/bindings/gpio/ti,twl4030-gpio.yaml‎

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@@ -1,7 +1,7 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ti,twl4030-gpio.yaml#
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$id: http://devicetree.org/schemas/gpio/ti,twl4030-gpio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI TWL4030 GPIO controller

‎Documentation/devicetree/bindings/spi/spi-cadence.yaml‎

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@@ -21,6 +21,7 @@ properties:
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- enum:
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- xlnx,zynqmp-spi-r1p6
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- xlnx,versal-net-spi-r1p6
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- cix,sky1-spi-r1p6
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- const: cdns,spi-r1p6
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reg:

‎Documentation/firmware-guide/acpi/i2c-muxes.rst‎

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@@ -37,8 +37,8 @@ which corresponds to the following ASL (in the scope of \_SB)::
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Name (_HID, ...)
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Name (_CRS, ResourceTemplate () {
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I2cSerialBus (0x50, ControllerInitiated, I2C_SPEED,
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AddressingMode7Bit, "\\_SB.SMB1.CH00", 0x00,
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ResourceConsumer,,)
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AddressingMode7Bit, "\\_SB.SMB1.MUX0.CH00",
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0x00, ResourceConsumer,,)
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}
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}
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}
@@ -52,8 +52,8 @@ which corresponds to the following ASL (in the scope of \_SB)::
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Name (_HID, ...)
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Name (_CRS, ResourceTemplate () {
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I2cSerialBus (0x50, ControllerInitiated, I2C_SPEED,
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AddressingMode7Bit, "\\_SB.SMB1.CH01", 0x00,
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ResourceConsumer,,)
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AddressingMode7Bit, "\\_SB.SMB1.MUX0.CH01",
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0x00, ResourceConsumer,,)
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}
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}
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}

‎MAINTAINERS‎

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@@ -4818,6 +4818,7 @@ F: drivers/net/dsa/b53/*
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F: drivers/net/dsa/bcm_sf2*
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F: include/linux/dsa/brcm.h
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F: include/linux/platform_data/b53.h
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F: net/dsa/tag_brcm.c
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BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
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M: Florian Fainelli <florian.fainelli@broadcom.com>
@@ -12521,6 +12522,7 @@ F: include/linux/avf/virtchnl.h
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F: include/linux/net/intel/*/
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INTEL ETHERNET PROTOCOL DRIVER FOR RDMA
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M: Krzysztof Czurylo <krzysztof.czurylo@intel.com>
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M: Tatyana Nikolova <tatyana.e.nikolova@intel.com>
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L: linux-rdma@vger.kernel.org
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S: Supported
@@ -12861,7 +12863,8 @@ F: tools/testing/selftests/sgx/*
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K: \bSGX_
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INTEL SKYLAKE INT3472 ACPI DEVICE DRIVER
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M: Daniel Scally <djrscally@gmail.com>
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M: Daniel Scally <dan.scally@ideasonboard.com>
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M: Sakari Ailus <sakari.ailus@linux.intel.com>
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S: Maintained
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F: drivers/platform/x86/intel/int3472/
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F: include/linux/platform_data/x86/int3472.h
@@ -20160,6 +20163,7 @@ R: Alexander Shishkin <alexander.shishkin@linux.intel.com>
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R: Jiri Olsa <jolsa@kernel.org>
2016120164
R: Ian Rogers <irogers@google.com>
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R: Adrian Hunter <adrian.hunter@intel.com>
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R: James Clark <james.clark@linaro.org>
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L: linux-perf-users@vger.kernel.org
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L: linux-kernel@vger.kernel.org
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S: Supported

‎Makefile‎

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@@ -2,7 +2,7 @@
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VERSION = 6
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PATCHLEVEL = 18
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SUBLEVEL = 0
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EXTRAVERSION = -rc4
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EXTRAVERSION = -rc5
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NAME = Baby Opossum Posse
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# *DOCUMENTATION*

‎arch/Kconfig‎

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@@ -917,6 +917,13 @@ config ARCH_USES_CFI_TRAPS
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An architecture should select this option if it requires the
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.kcfi_traps section for KCFI trap handling.
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config ARCH_USES_CFI_GENERIC_LLVM_PASS
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bool
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help
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An architecture should select this option if it uses the generic
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KCFIPass in LLVM to expand kCFI bundles instead of architecture-specific
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lowering.
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config CFI
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bool "Use Kernel Control Flow Integrity (kCFI)"
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default CFI_CLANG

‎arch/arm/Kconfig‎

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select ARCH_USE_BUILTIN_BSWAP
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select ARCH_USE_CMPXCHG_LOCKREF
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select ARCH_USE_MEMTEST
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# https://github.com/llvm/llvm-project/commit/d130f402642fba3d065aacb506cb061c899558de
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select ARCH_USES_CFI_GENERIC_LLVM_PASS if CLANG_VERSION < 220000
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select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
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select ARCH_WANT_GENERAL_HUGETLB
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select ARCH_WANT_IPC_PARSE_VERSION

‎arch/loongarch/Makefile‎

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@@ -109,7 +109,7 @@ endif
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ifdef CONFIG_RUSTC_HAS_ANNOTATE_TABLEJUMP
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KBUILD_RUSTFLAGS += -Cllvm-args=--loongarch-annotate-tablejump
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else
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KBUILD_RUSTFLAGS += -Zno-jump-tables # keep compatibility with older compilers
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KBUILD_RUSTFLAGS += $(if $(call rustc-min-version,109300),-Cjump-tables=n,-Zno-jump-tables) # keep compatibility with older compilers
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endif
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ifdef CONFIG_LTO_CLANG
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# The annotate-tablejump option can not be passed to LLVM backend when LTO is enabled.

‎arch/parisc/kernel/unwind.c‎

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@@ -35,6 +35,8 @@
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#define KERNEL_START (KERNEL_BINARY_TEXT_START)
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#define ALIGNMENT_OK(ptr, type) (((ptr) & (sizeof(type) - 1)) == 0)
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extern struct unwind_table_entry __start___unwind[];
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extern struct unwind_table_entry __stop___unwind[];
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if (pc_is_kernel_fn(pc, _switch_to) ||
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pc == (unsigned long)&_switch_to_ret) {
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info->prev_sp = info->sp - CALLEE_SAVE_FRAME_SIZE;
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info->prev_ip = *(unsigned long *)(info->prev_sp - RP_OFFSET);
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if (ALIGNMENT_OK(info->prev_sp, long))
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info->prev_ip = *(unsigned long *)(info->prev_sp - RP_OFFSET);
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else
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info->prev_ip = info->prev_sp = 0;
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return 1;
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}
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#ifdef CONFIG_IRQSTACKS
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if (pc == (unsigned long)&_call_on_stack) {
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if (pc == (unsigned long)&_call_on_stack && ALIGNMENT_OK(info->sp, long)) {
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info->prev_sp = *(unsigned long *)(info->sp - FRAME_SIZE - REG_SZ);
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info->prev_ip = *(unsigned long *)(info->sp - FRAME_SIZE - RP_OFFSET);
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return 1;
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info->prev_sp = info->sp - frame_size;
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if (e->Millicode)
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info->rp = info->r31;
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else if (rpoffset)
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else if (rpoffset && ALIGNMENT_OK(info->prev_sp, long))
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info->rp = *(unsigned long *)(info->prev_sp - rpoffset);
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else
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info->rp = 0;
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info->prev_ip = info->rp;
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info->rp = 0;
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}

‎arch/riscv/include/asm/asm.h‎

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#define __ASM_STR(x) #x
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#endif
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#ifdef CONFIG_AS_HAS_INSN
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#define ASM_INSN_I(__x) ".insn " __x
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#else
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#define ASM_INSN_I(__x) ".4byte " __x
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#endif
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#if __riscv_xlen == 64
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#define __REG_SEL(a, b) __ASM_STR(a)
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#elif __riscv_xlen == 32

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