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clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register
This register is important for sequencing the commands to PLLs, so actually write the update bits with regmap_write_bits() instead of relying on a read/modify/write regmap command that could skip the actual hardware write if the value is identical to the one read. It's changed when modification is needed to the PLL, when read-only operation is done, we could keep the call to regmap_update_bits(). Add a comment to the sam9x60_div_pll_set_div() function that uses this PLL_UPDT register so that it's used consistently, according to the product's datasheet. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Tested-by: Ryan Wanner <ryan.wanner@microchip.com> # on sama7d65 and sam9x75 Link: https://lore.kernel.org/r/20250827150811.82496-1-nicolas.ferre@microchip.com [claudiu.beznea: fix "Alignment should match open parenthesis" checkpatch.pl check] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
1 parent 0c01fe4 commit af98cae

1 file changed

Lines changed: 39 additions & 36 deletions

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‎drivers/clk/at91/clk-sam9x60-pll.c‎

Lines changed: 39 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -93,8 +93,8 @@ static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
9393

9494
spin_lock_irqsave(core->lock, flags);
9595

96-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
97-
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
96+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
97+
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
9898
regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
9999
cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
100100
cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
@@ -128,17 +128,17 @@ static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
128128
udelay(10);
129129
}
130130

131-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
132-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
133-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
131+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
132+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
133+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
134134

135135
regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
136136
AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
137137
AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL);
138138

139-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
140-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
141-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
139+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
140+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
141+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
142142

143143
while (!sam9x60_pll_ready(regmap, core->id))
144144
cpu_relax();
@@ -164,18 +164,18 @@ static void sam9x60_frac_pll_unprepare(struct clk_hw *hw)
164164

165165
spin_lock_irqsave(core->lock, flags);
166166

167-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
168-
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
167+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
168+
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
169169

170170
regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, AT91_PMC_PLL_CTRL0_ENPLL, 0);
171171

172172
if (core->characteristics->upll)
173173
regmap_update_bits(regmap, AT91_PMC_PLL_ACR,
174174
AT91_PMC_PLL_ACR_UTMIBG | AT91_PMC_PLL_ACR_UTMIVR, 0);
175175

176-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
177-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
178-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
176+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
177+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
178+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
179179

180180
spin_unlock_irqrestore(core->lock, flags);
181181
}
@@ -262,8 +262,8 @@ static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
262262

263263
spin_lock_irqsave(core->lock, irqflags);
264264

265-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
266-
core->id);
265+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
266+
core->id);
267267
regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
268268
cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
269269
cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
@@ -275,18 +275,18 @@ static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
275275
(frac->mul << core->layout->mul_shift) |
276276
(frac->frac << core->layout->frac_shift));
277277

278-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
279-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
280-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
278+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
279+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
280+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
281281

282282
regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
283283
AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
284284
AT91_PMC_PLL_CTRL0_ENLOCK |
285285
AT91_PMC_PLL_CTRL0_ENPLL);
286286

287-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
288-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
289-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
287+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
288+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
289+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
290290

291291
while (!sam9x60_pll_ready(regmap, core->id))
292292
cpu_relax();
@@ -338,7 +338,10 @@ static const struct clk_ops sam9x60_frac_pll_ops_chg = {
338338
.restore_context = sam9x60_frac_pll_restore_context,
339339
};
340340

341-
/* This function should be called with spinlock acquired. */
341+
/* This function should be called with spinlock acquired.
342+
* Warning: this function must be called only if the same PLL ID was set in
343+
* PLL_UPDT register previously.
344+
*/
342345
static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div,
343346
bool enable)
344347
{
@@ -350,9 +353,9 @@ static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div,
350353
core->layout->div_mask | ena_msk,
351354
(div << core->layout->div_shift) | ena_val);
352355

353-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
354-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
355-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
356+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
357+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
358+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
356359

357360
while (!sam9x60_pll_ready(regmap, core->id))
358361
cpu_relax();
@@ -366,8 +369,8 @@ static int sam9x60_div_pll_set(struct sam9x60_pll_core *core)
366369
unsigned int val, cdiv;
367370

368371
spin_lock_irqsave(core->lock, flags);
369-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
370-
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
372+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
373+
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
371374
regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
372375
cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
373376

@@ -398,15 +401,15 @@ static void sam9x60_div_pll_unprepare(struct clk_hw *hw)
398401

399402
spin_lock_irqsave(core->lock, flags);
400403

401-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
402-
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
404+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
405+
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
403406

404407
regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
405408
core->layout->endiv_mask, 0);
406409

407-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
408-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
409-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
410+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
411+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
412+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
410413

411414
spin_unlock_irqrestore(core->lock, flags);
412415
}
@@ -518,8 +521,8 @@ static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
518521
div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
519522

520523
spin_lock_irqsave(core->lock, irqflags);
521-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
522-
core->id);
524+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
525+
core->id);
523526
regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
524527
cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
525528

@@ -574,8 +577,8 @@ static int sam9x60_div_pll_notifier_fn(struct notifier_block *notifier,
574577
div->div = div->safe_div;
575578

576579
spin_lock_irqsave(core.lock, irqflags);
577-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
578-
core.id);
580+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
581+
core.id);
579582
regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
580583
cdiv = (val & core.layout->div_mask) >> core.layout->div_shift;
581584

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