riscv: traps_misaligned: properly sign extend value in misaligned load handler

andreas-schwab · palmer-dabbelt · commit b3510183ab7d · 2025-07-16T09:05:39.000-07:00
Add missing cast to signed long. Signed-off-by: Andreas Schwab <schwab@suse.de> Fixes: 956d705 ("riscv: Unaligned load/store handling for M_MODE") Tested-by: Clément Léger <cleger@rivosinc.com> Link: https://lore.kernel.org/r/mvmikk0goil.fsf@suse.de Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
@@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)
 	}
 
 	if (!fp)
-		SET_RD(insn, regs, val.data_ulong << shift >> shift);
+		SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift);
 	else if (len == 8)
 		set_f64_rd(insn, regs, val.data_u64);
 	else

Original file line number	Diff line number	Diff line change
`@@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)`
`461`	`461`	`}`
`462`	`462`
`463`	`463`	`if (!fp)`
`464`		`- SET_RD(insn, regs, val.data_ulong << shift >> shift);`
	`464`	`+ SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift);`
`465`	`465`	`else if (len == 8)`
`466`	`466`	`set_f64_rd(insn, regs, val.data_u64);`
`467`	`467`	`else`