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clementlegeravpatel
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RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG
SBI_FWFT_MISALIGNED_DELEG needs hedeleg to be modified to delegate misaligned load/store exceptions. Save and restore it during CPU load/put. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Deepak Gupta <debug@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20250523101932.1594077-15-cleger@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
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arch/riscv/kvm/vcpu_sbi_fwft.c

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@@ -14,6 +14,8 @@
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#include <asm/kvm_vcpu_sbi.h>
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#include <asm/kvm_vcpu_sbi_fwft.h>
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#define MIS_DELEG (BIT_ULL(EXC_LOAD_MISALIGNED) | BIT_ULL(EXC_STORE_MISALIGNED))
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struct kvm_sbi_fwft_feature {
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/**
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* @id: Feature ID
@@ -68,7 +70,46 @@ static bool kvm_fwft_is_defined_feature(enum sbi_fwft_feature_t feature)
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return false;
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}
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static bool kvm_sbi_fwft_misaligned_delegation_supported(struct kvm_vcpu *vcpu)
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{
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return misaligned_traps_can_delegate();
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}
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static long kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu,
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struct kvm_sbi_fwft_config *conf,
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unsigned long value)
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{
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struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
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if (value == 1) {
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cfg->hedeleg |= MIS_DELEG;
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csr_set(CSR_HEDELEG, MIS_DELEG);
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} else if (value == 0) {
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cfg->hedeleg &= ~MIS_DELEG;
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csr_clear(CSR_HEDELEG, MIS_DELEG);
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} else {
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return SBI_ERR_INVALID_PARAM;
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}
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return SBI_SUCCESS;
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}
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static long kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu,
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struct kvm_sbi_fwft_config *conf,
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unsigned long *value)
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{
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*value = (csr_read(CSR_HEDELEG) & MIS_DELEG) == MIS_DELEG;
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return SBI_SUCCESS;
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}
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static const struct kvm_sbi_fwft_feature features[] = {
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{
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.id = SBI_FWFT_MISALIGNED_EXC_DELEG,
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.supported = kvm_sbi_fwft_misaligned_delegation_supported,
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.set = kvm_sbi_fwft_set_misaligned_delegation,
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.get = kvm_sbi_fwft_get_misaligned_delegation,
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},
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};
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static struct kvm_sbi_fwft_config *

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