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| 1 | +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/interconnect/qcom,glymur-rpmh.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Qualcomm RPMh Network-On-Chip Interconnect on GLYMUR |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> |
| 11 | + |
| 12 | +description: | |
| 13 | + RPMh interconnect providers support system bandwidth requirements through |
| 14 | + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is |
| 15 | + able to communicate with the BCM through the Resource State Coordinator (RSC) |
| 16 | + associated with each execution environment. Provider nodes must point to at |
| 17 | + least one RPMh device child node pertaining to their RSC and each provider |
| 18 | + can map to multiple RPMh resources. |
| 19 | +
|
| 20 | + See also: include/dt-bindings/interconnect/qcom,glymur-rpmh.h |
| 21 | +
|
| 22 | +properties: |
| 23 | + compatible: |
| 24 | + enum: |
| 25 | + - qcom,glymur-aggre1-noc |
| 26 | + - qcom,glymur-aggre2-noc |
| 27 | + - qcom,glymur-aggre3-noc |
| 28 | + - qcom,glymur-aggre4-noc |
| 29 | + - qcom,glymur-clk-virt |
| 30 | + - qcom,glymur-cnoc-cfg |
| 31 | + - qcom,glymur-cnoc-main |
| 32 | + - qcom,glymur-hscnoc |
| 33 | + - qcom,glymur-lpass-ag-noc |
| 34 | + - qcom,glymur-lpass-lpiaon-noc |
| 35 | + - qcom,glymur-lpass-lpicx-noc |
| 36 | + - qcom,glymur-mc-virt |
| 37 | + - qcom,glymur-mmss-noc |
| 38 | + - qcom,glymur-nsinoc |
| 39 | + - qcom,glymur-nsp-noc |
| 40 | + - qcom,glymur-oobm-ss-noc |
| 41 | + - qcom,glymur-pcie-east-anoc |
| 42 | + - qcom,glymur-pcie-east-slv-noc |
| 43 | + - qcom,glymur-pcie-west-anoc |
| 44 | + - qcom,glymur-pcie-west-slv-noc |
| 45 | + - qcom,glymur-system-noc |
| 46 | + |
| 47 | + reg: |
| 48 | + maxItems: 1 |
| 49 | + |
| 50 | + clocks: |
| 51 | + minItems: 1 |
| 52 | + maxItems: 4 |
| 53 | + |
| 54 | +required: |
| 55 | + - compatible |
| 56 | + |
| 57 | +allOf: |
| 58 | + - $ref: qcom,rpmh-common.yaml# |
| 59 | + - if: |
| 60 | + properties: |
| 61 | + compatible: |
| 62 | + contains: |
| 63 | + enum: |
| 64 | + - qcom,glymur-clk-virt |
| 65 | + - qcom,glymur-mc-virt |
| 66 | + then: |
| 67 | + properties: |
| 68 | + reg: false |
| 69 | + else: |
| 70 | + required: |
| 71 | + - reg |
| 72 | + |
| 73 | + - if: |
| 74 | + properties: |
| 75 | + compatible: |
| 76 | + contains: |
| 77 | + enum: |
| 78 | + - qcom,glymur-pcie-west-anoc |
| 79 | + then: |
| 80 | + properties: |
| 81 | + clocks: |
| 82 | + items: |
| 83 | + - description: aggre PCIE_3A WEST AXI clock |
| 84 | + - description: aggre PCIE_3B WEST AXI clock |
| 85 | + - description: aggre PCIE_4 WEST AXI clock |
| 86 | + - description: aggre PCIE_6 WEST AXI clock |
| 87 | + |
| 88 | + - if: |
| 89 | + properties: |
| 90 | + compatible: |
| 91 | + contains: |
| 92 | + enum: |
| 93 | + - qcom,glymur-pcie-east-anoc |
| 94 | + then: |
| 95 | + properties: |
| 96 | + clocks: |
| 97 | + items: |
| 98 | + - description: aggre PCIE_5 EAST AXI clock |
| 99 | + |
| 100 | + - if: |
| 101 | + properties: |
| 102 | + compatible: |
| 103 | + contains: |
| 104 | + enum: |
| 105 | + - qcom,glymur-aggre2-noc |
| 106 | + then: |
| 107 | + properties: |
| 108 | + clocks: |
| 109 | + items: |
| 110 | + - description: aggre USB3 TERT AXI clock |
| 111 | + - description: aggre USB4_2 AXI clock |
| 112 | + - description: aggre UFS PHY AXI clock |
| 113 | + |
| 114 | + - if: |
| 115 | + properties: |
| 116 | + compatible: |
| 117 | + contains: |
| 118 | + enum: |
| 119 | + - qcom,glymur-aggre4-noc |
| 120 | + then: |
| 121 | + properties: |
| 122 | + clocks: |
| 123 | + items: |
| 124 | + - description: aggre USB3 PRIM AXI clock |
| 125 | + - description: aggre USB3 SEC AXI clock |
| 126 | + - description: aggre USB4_0 AXI clock |
| 127 | + - description: aggre USB4_1 AXI clock |
| 128 | + |
| 129 | + - if: |
| 130 | + properties: |
| 131 | + compatible: |
| 132 | + contains: |
| 133 | + enum: |
| 134 | + - qcom,glymur-pcie-west-anoc |
| 135 | + - qcom,glymur-pcie-east-anoc |
| 136 | + - qcom,glymur-aggre2-noc |
| 137 | + - qcom,glymur-aggre4-noc |
| 138 | + then: |
| 139 | + required: |
| 140 | + - clocks |
| 141 | + else: |
| 142 | + properties: |
| 143 | + clocks: false |
| 144 | + |
| 145 | +unevaluatedProperties: false |
| 146 | + |
| 147 | +examples: |
| 148 | + - | |
| 149 | + #include <dt-bindings/clock/qcom,glymur-gcc.h> |
| 150 | + clk_virt: interconnect-0 { |
| 151 | + compatible = "qcom,glymur-clk-virt"; |
| 152 | + #interconnect-cells = <2>; |
| 153 | + qcom,bcm-voters = <&apps_bcm_voter>; |
| 154 | + }; |
| 155 | +
|
| 156 | + aggre1_noc: interconnect@16e0000 { |
| 157 | + compatible = "qcom,glymur-aggre1-noc"; |
| 158 | + reg = <0x016e0000 0x14400>; |
| 159 | + #interconnect-cells = <2>; |
| 160 | + qcom,bcm-voters = <&apps_bcm_voter>; |
| 161 | + }; |
| 162 | +
|
| 163 | + aggre4_noc: interconnect@1740000 { |
| 164 | + compatible = "qcom,glymur-aggre4-noc"; |
| 165 | + reg = <0x01740000 0x14400>; |
| 166 | + #interconnect-cells = <2>; |
| 167 | + qcom,bcm-voters = <&apps_bcm_voter>; |
| 168 | + clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, |
| 169 | + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, |
| 170 | + <&gcc GCC_AGGRE_USB4_0_AXI_CLK>, |
| 171 | + <&gcc GCC_AGGRE_USB4_1_AXI_CLK>; |
| 172 | + }; |
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