Skip to content

Commit c1abbe6

Browse files
arndbarndb
committed
Merge tag 'v6.15-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
New peripheral the sdhci controller on rk3528. Enablement of hdmi and hdmi audio on a number of additional boards. Better handling for scmi shared memory on rk3568 and a fix for the used SCMI clock ids on rk3576. As well as some fixes that were a bit late for trying to stuff them into 6.14 at this late stage of the cycle. * tag 'v6.15-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: remove ethm0_clk0_25m_out from Sige5 gmac0 arm64: dts: rockchip: Fix PWM pinctrl names arm64: dts: rockchip: fix RK3576 SCMI clock IDs dt-bindings: clock: rk3576: add SCMI clocks arm64: dts: rockchip: Fix pcie reset gpio on Orange Pi 5 Max arm64: dts: rockchip: Enable HDMI audio output for ArmSoM Sige7 arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C arm64: dts: rockchip: Add SDHCI controller for RK3528 arm64: dts: rockchip: Remove bluetooth node from rock-3a arm64: dts: rockchip: Move rk356x scmi SHMEM to reserved memory arm64: dts: rockchip: Add AP6275P wireless support to ArmSoM Sige7 arm64: dts: rockchip: Enable HDMI audio outputs for Orange Pi 5 Plus arm64: dts: rockchip: Enable HDMI1 on Orange Pi 5 Plus arm64: dts: rockchip: Enable HDMI audio outputs for Orange Pi 5 Max arm64: dts: rockchip: Enable HDMI0 audio output for Orange Pi 5/5B Link: https://lore.kernel.org/r/23866869.6Emhk5qWAg@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents a1b4678 + 73d246b commit c1abbe6

16 files changed

Lines changed: 174 additions & 44 deletions

‎arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -147,7 +147,7 @@
147147

148148
&pwm5 {
149149
status = "okay";
150-
pinctrl-names = "active";
150+
pinctrl-names = "default";
151151
pinctrl-0 = <&pwm5_pin_pull_down>;
152152
};
153153

‎arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -274,13 +274,13 @@
274274

275275
&pwm0 {
276276
pinctrl-0 = <&pwm0_pin_pull_up>;
277-
pinctrl-names = "active";
277+
pinctrl-names = "default";
278278
status = "okay";
279279
};
280280

281281
&pwm1 {
282282
pinctrl-0 = <&pwm1_pin_pull_up>;
283-
pinctrl-names = "active";
283+
pinctrl-names = "default";
284284
status = "okay";
285285
};
286286

‎arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -603,7 +603,7 @@
603603
};
604604

605605
&pwm2 {
606-
pinctrl-names = "active";
606+
pinctrl-names = "default";
607607
pinctrl-0 = <&pwm2_pin_pull_down>;
608608
status = "okay";
609609
};

‎arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,10 @@
1515
model = "Radxa E20C";
1616
compatible = "radxa,e20c", "rockchip,rk3528";
1717

18+
aliases {
19+
mmc0 = &sdhci;
20+
};
21+
1822
chosen {
1923
stdout-path = "serial0:1500000n8";
2024
};
@@ -133,6 +137,17 @@
133137
status = "okay";
134138
};
135139

140+
&sdhci {
141+
bus-width = <8>;
142+
cap-mmc-highspeed;
143+
no-sd;
144+
no-sdio;
145+
non-removable;
146+
vmmc-supply = <&vcc_3v3>;
147+
vqmmc-supply = <&vcc_1v8>;
148+
status = "okay";
149+
};
150+
136151
&uart0 {
137152
pinctrl-names = "default";
138153
pinctrl-0 = <&uart0m0_xfer>;

‎arch/arm64/boot/dts/rockchip/rk3528.dtsi‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -468,6 +468,30 @@
468468
status = "disabled";
469469
};
470470

471+
sdhci: mmc@ffbf0000 {
472+
compatible = "rockchip,rk3528-dwcmshc",
473+
"rockchip,rk3588-dwcmshc";
474+
reg = <0x0 0xffbf0000 0x0 0x10000>;
475+
assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
476+
<&cru CCLK_SRC_EMMC>;
477+
assigned-clock-rates = <200000000>, <24000000>,
478+
<200000000>;
479+
clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
480+
<&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
481+
<&cru TCLK_EMMC>;
482+
clock-names = "core", "bus", "axi", "block", "timer";
483+
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
484+
max-frequency = <200000000>;
485+
pinctrl-names = "default";
486+
pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
487+
<&emmc_strb>;
488+
resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
489+
<&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
490+
<&cru SRST_T_EMMC>;
491+
reset-names = "core", "bus", "axi", "block", "timer";
492+
status = "disabled";
493+
};
494+
471495
pinctrl: pinctrl {
472496
compatible = "rockchip,rk3528-pinctrl";
473497
rockchip,grf = <&ioc_grf>;

‎arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts‎

Lines changed: 0 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -778,20 +778,6 @@
778778
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
779779
uart-has-rtscts;
780780
status = "okay";
781-
782-
bluetooth {
783-
compatible = "brcm,bcm43438-bt";
784-
clocks = <&rk809 1>;
785-
clock-names = "lpo";
786-
device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
787-
host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
788-
shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
789-
pinctrl-names = "default";
790-
pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>;
791-
vbat-supply = <&vcc3v3_sys>;
792-
vddio-supply = <&vcc_1v8>;
793-
/* vddio comes from regulator on module, use IO bank voltage instead */
794-
};
795781
};
796782

797783
&uart2 {

‎arch/arm64/boot/dts/rockchip/rk356x-base.dtsi‎

Lines changed: 12 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -174,6 +174,18 @@
174174
method = "smc";
175175
};
176176

177+
reserved-memory {
178+
#address-cells = <2>;
179+
#size-cells = <2>;
180+
ranges;
181+
182+
scmi_shmem: shmem@10f000 {
183+
compatible = "arm,scmi-shmem";
184+
reg = <0x0 0x0010f000 0x0 0x100>;
185+
no-map;
186+
};
187+
};
188+
177189
timer {
178190
compatible = "arm,armv8-timer";
179191
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
@@ -199,19 +211,6 @@
199211
#clock-cells = <0>;
200212
};
201213

202-
sram@10f000 {
203-
compatible = "mmio-sram";
204-
reg = <0x0 0x0010f000 0x0 0x100>;
205-
#address-cells = <1>;
206-
#size-cells = <1>;
207-
ranges = <0 0x0 0x0010f000 0x100>;
208-
209-
scmi_shmem: sram@0 {
210-
compatible = "arm,scmi-shmem";
211-
reg = <0x0 0x100>;
212-
};
213-
};
214-
215214
sata1: sata@fc400000 {
216215
compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
217216
reg = <0 0xfc400000 0 0x1000>;

‎arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -194,8 +194,7 @@
194194
&eth0m0_tx_bus2
195195
&eth0m0_rx_bus2
196196
&eth0m0_rgmii_clk
197-
&eth0m0_rgmii_bus
198-
&ethm0_clk0_25m_out>;
197+
&eth0m0_rgmii_bus>;
199198

200199
phy-handle = <&rgmii_phy0>;
201200
status = "okay";

‎arch/arm64/boot/dts/rockchip/rk3576.dtsi‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -111,7 +111,7 @@
111111
reg = <0x0>;
112112
enable-method = "psci";
113113
capacity-dmips-mhz = <485>;
114-
clocks = <&scmi_clk ARMCLK_L>;
114+
clocks = <&scmi_clk SCMI_ARMCLK_L>;
115115
operating-points-v2 = <&cluster0_opp_table>;
116116
#cooling-cells = <2>;
117117
dynamic-power-coefficient = <120>;
@@ -124,7 +124,7 @@
124124
reg = <0x1>;
125125
enable-method = "psci";
126126
capacity-dmips-mhz = <485>;
127-
clocks = <&scmi_clk ARMCLK_L>;
127+
clocks = <&scmi_clk SCMI_ARMCLK_L>;
128128
operating-points-v2 = <&cluster0_opp_table>;
129129
cpu-idle-states = <&CPU_SLEEP>;
130130
};
@@ -135,7 +135,7 @@
135135
reg = <0x2>;
136136
enable-method = "psci";
137137
capacity-dmips-mhz = <485>;
138-
clocks = <&scmi_clk ARMCLK_L>;
138+
clocks = <&scmi_clk SCMI_ARMCLK_L>;
139139
operating-points-v2 = <&cluster0_opp_table>;
140140
cpu-idle-states = <&CPU_SLEEP>;
141141
};
@@ -146,7 +146,7 @@
146146
reg = <0x3>;
147147
enable-method = "psci";
148148
capacity-dmips-mhz = <485>;
149-
clocks = <&scmi_clk ARMCLK_L>;
149+
clocks = <&scmi_clk SCMI_ARMCLK_L>;
150150
operating-points-v2 = <&cluster0_opp_table>;
151151
cpu-idle-states = <&CPU_SLEEP>;
152152
};
@@ -157,7 +157,7 @@
157157
reg = <0x100>;
158158
enable-method = "psci";
159159
capacity-dmips-mhz = <1024>;
160-
clocks = <&scmi_clk ARMCLK_B>;
160+
clocks = <&scmi_clk SCMI_ARMCLK_B>;
161161
operating-points-v2 = <&cluster1_opp_table>;
162162
#cooling-cells = <2>;
163163
dynamic-power-coefficient = <320>;
@@ -170,7 +170,7 @@
170170
reg = <0x101>;
171171
enable-method = "psci";
172172
capacity-dmips-mhz = <1024>;
173-
clocks = <&scmi_clk ARMCLK_B>;
173+
clocks = <&scmi_clk SCMI_ARMCLK_B>;
174174
operating-points-v2 = <&cluster1_opp_table>;
175175
cpu-idle-states = <&CPU_SLEEP>;
176176
};
@@ -181,7 +181,7 @@
181181
reg = <0x102>;
182182
enable-method = "psci";
183183
capacity-dmips-mhz = <1024>;
184-
clocks = <&scmi_clk ARMCLK_B>;
184+
clocks = <&scmi_clk SCMI_ARMCLK_B>;
185185
operating-points-v2 = <&cluster1_opp_table>;
186186
cpu-idle-states = <&CPU_SLEEP>;
187187
};
@@ -192,7 +192,7 @@
192192
reg = <0x103>;
193193
enable-method = "psci";
194194
capacity-dmips-mhz = <1024>;
195-
clocks = <&scmi_clk ARMCLK_B>;
195+
clocks = <&scmi_clk SCMI_ARMCLK_B>;
196196
operating-points-v2 = <&cluster1_opp_table>;
197197
cpu-idle-states = <&CPU_SLEEP>;
198198
};
@@ -932,7 +932,7 @@
932932
gpu: gpu@27800000 {
933933
compatible = "rockchip,rk3576-mali", "arm,mali-bifrost";
934934
reg = <0x0 0x27800000 0x0 0x200000>;
935-
assigned-clocks = <&scmi_clk CLK_GPU>;
935+
assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
936936
assigned-clock-rates = <198000000>;
937937
clocks = <&cru CLK_GPU>;
938938
clock-names = "core";

‎arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -192,6 +192,10 @@
192192
};
193193
};
194194

195+
&hdmi0_sound {
196+
status = "okay";
197+
};
198+
195199
&hdptxphy0 {
196200
status = "okay";
197201
};
@@ -290,6 +294,10 @@
290294
};
291295
};
292296

297+
&i2s5_8ch {
298+
status = "okay";
299+
};
300+
293301
/* phy1 - right ethernet port */
294302
&pcie2x1l0 {
295303
reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
@@ -300,6 +308,22 @@
300308
&pcie2x1l1 {
301309
reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
302310
status = "okay";
311+
312+
pcie@0,0 {
313+
reg = <0x300000 0 0 0 0>;
314+
#address-cells = <3>;
315+
#size-cells = <2>;
316+
ranges;
317+
device_type = "pci";
318+
bus-range = <0x30 0x3f>;
319+
320+
wifi: wifi@0,0 {
321+
compatible = "pci14e4,449d";
322+
reg = <0x310000 0 0 0 0>;
323+
clocks = <&hym8563>;
324+
clock-names = "lpo";
325+
};
326+
};
303327
};
304328

305329
/* phy0 - left ethernet port */

0 commit comments

Comments
 (0)