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Merge tag 'renesas-dts-for-v6.14-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.14 (take two) - Add pin control support for the RZ/G3E SoC and the RZ/G3E SMARC Carrier-II EVK development board, - Add Image Signal Processor helper block (FCPVX and VSPX) support for the R-Car V4H SoC, - Describe odd C-PHY wiring on the White Hawk CSI/DSI sub-board, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.14-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: white-hawk-csi-dsi: Define CSI-2 data line orders arm64: dts: renesas: r8a779g0: Add VSPX instances arm64: dts: renesas: r8a779g0: Add FCPVX instances arm64: dts: renesas: r9a09g047e57-smarc: Add SCIF pincontrol arm64: dts: renesas: r9a09g047: Add pincontrol node arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Replace RZG2L macros dt-bindings: pinctrl: renesas: Document RZ/G3E SoC dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H Link: https://lore.kernel.org/r/cover.1736180859.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents 608e9fe + c357e22 commit c50a335

8 files changed

Lines changed: 163 additions & 20 deletions

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‎Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@ properties:
2626
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
2727
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
2828
- renesas,r9a08g045-pinctrl # RZ/G3S
29+
- renesas,r9a09g047-pinctrl # RZ/G3E
2930
- renesas,r9a09g057-pinctrl # RZ/V2H(P)
3031

3132
- items:
@@ -125,7 +126,7 @@ additionalProperties:
125126
drive-push-pull: true
126127
renesas,output-impedance:
127128
description:
128-
Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this
129+
Output impedance for pins on the RZ/{G3E,V2H(P)} SoC. The value provided by this
129130
property corresponds to register bit values that can be set in the PFC_IOLH_mn
130131
register, which adjusts the drive strength value and is pin-dependent.
131132
$ref: /schemas/types.yaml#/definitions/uint32
@@ -142,7 +143,9 @@ allOf:
142143
properties:
143144
compatible:
144145
contains:
145-
const: renesas,r9a09g057-pinctrl
146+
enum:
147+
- renesas,r9a09g047-pinctrl
148+
- renesas,r9a09g057-pinctrl
146149
then:
147150
properties:
148151
resets:

‎arch/arm64/boot/dts/renesas/r8a779g0.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -2453,6 +2453,46 @@
24532453
};
24542454
};
24552455

2456+
fcpvx0: fcp@fedb0000 {
2457+
compatible = "renesas,fcpv";
2458+
reg = <0 0xfedb0000 0 0x200>;
2459+
clocks = <&cpg CPG_MOD 1100>;
2460+
power-domains = <&sysc R8A779G0_PD_A3ISP0>;
2461+
resets = <&cpg 1100>;
2462+
iommus = <&ipmmu_vi1 24>;
2463+
};
2464+
2465+
fcpvx1: fcp@fedb8000 {
2466+
compatible = "renesas,fcpv";
2467+
reg = <0 0xfedb8000 0 0x200>;
2468+
clocks = <&cpg CPG_MOD 1101>;
2469+
power-domains = <&sysc R8A779G0_PD_A3ISP1>;
2470+
resets = <&cpg 1101>;
2471+
iommus = <&ipmmu_vi1 25>;
2472+
};
2473+
2474+
vspx0: vsp@fedd0000 {
2475+
compatible = "renesas,vsp2";
2476+
reg = <0 0xfedd0000 0 0x8000>;
2477+
interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>;
2478+
clocks = <&cpg CPG_MOD 1028>;
2479+
power-domains = <&sysc R8A779G0_PD_A3ISP0>;
2480+
resets = <&cpg 1028>;
2481+
2482+
renesas,fcp = <&fcpvx0>;
2483+
};
2484+
2485+
vspx1: vsp@fedd8000 {
2486+
compatible = "renesas,vsp2";
2487+
reg = <0 0xfedd8000 0 0x8000>;
2488+
interrupts = <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
2489+
clocks = <&cpg CPG_MOD 1029>;
2490+
power-domains = <&sysc R8A779G0_PD_A3ISP1>;
2491+
resets = <&cpg 1029>;
2492+
2493+
renesas,fcp = <&fcpvx1>;
2494+
};
2495+
24562496
prr: chipid@fff00044 {
24572497
compatible = "renesas,prr";
24582498
reg = <0 0xfff00044 0 4>;

‎arch/arm64/boot/dts/renesas/r9a09g047.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -131,6 +131,19 @@
131131
#size-cells = <2>;
132132
ranges;
133133

134+
pinctrl: pinctrl@10410000 {
135+
compatible = "renesas,r9a09g047-pinctrl";
136+
reg = <0 0x10410000 0 0x10000>;
137+
clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>;
138+
gpio-controller;
139+
#gpio-cells = <2>;
140+
gpio-ranges = <&pinctrl 0 0 232>;
141+
#interrupt-cells = <2>;
142+
interrupt-controller;
143+
power-domains = <&cpg>;
144+
resets = <&cpg 0xa5>, <&cpg 0xa6>;
145+
};
146+
134147
cpg: clock-controller@10420000 {
135148
compatible = "renesas,r9a09g047-cpg";
136149
reg = <0 0x10420000 0 0x10000>;

‎arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77

88
/dts-v1/;
99

10+
#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
1011
#include "r9a09g047e57.dtsi"
1112
#include "rzg3e-smarc-som.dtsi"
1213
#include "renesas-smarc2.dtsi"
@@ -16,3 +17,15 @@
1617
compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm",
1718
"renesas,r9a09g047e57", "renesas,r9a09g047";
1819
};
20+
21+
&pinctrl {
22+
scif_pins: scif {
23+
pins = "SCIF_TXD", "SCIF_RXD";
24+
renesas,output-impedance = <1>;
25+
};
26+
};
27+
28+
&scif0 {
29+
pinctrl-0 = <&scif_pins>;
30+
pinctrl-names = "default";
31+
};

‎arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77

88
/dts-v1/;
99

10-
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10+
#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
1111
#include <dt-bindings/gpio/gpio.h>
1212
#include "r9a09g057.dtsi"
1313

@@ -56,7 +56,7 @@
5656
vqmmc_sdhi1: regulator-vccq-sdhi1 {
5757
compatible = "regulator-gpio";
5858
regulator-name = "SDHI1 VccQ";
59-
gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>;
59+
gpios = <&pinctrl RZV2H_GPIO(A, 2) GPIO_ACTIVE_HIGH>;
6060
regulator-min-microvolt = <1800000>;
6161
regulator-max-microvolt = <3300000>;
6262
gpios-states = <0>;
@@ -158,38 +158,38 @@
158158

159159
&pinctrl {
160160
i2c0_pins: i2c0 {
161-
pinmux = <RZG2L_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */
162-
<RZG2L_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */
161+
pinmux = <RZV2H_PORT_PINMUX(3, 0, 1)>, /* I2C0_SDA */
162+
<RZV2H_PORT_PINMUX(3, 1, 1)>; /* I2C0_SCL */
163163
};
164164

165165
i2c1_pins: i2c1 {
166-
pinmux = <RZG2L_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */
167-
<RZG2L_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */
166+
pinmux = <RZV2H_PORT_PINMUX(3, 2, 1)>, /* I2C1_SDA */
167+
<RZV2H_PORT_PINMUX(3, 3, 1)>; /* I2C1_SCL */
168168
};
169169

170170
i2c2_pins: i2c2 {
171-
pinmux = <RZG2L_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */
172-
<RZG2L_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */
171+
pinmux = <RZV2H_PORT_PINMUX(2, 0, 4)>, /* I2C2_SDA */
172+
<RZV2H_PORT_PINMUX(2, 1, 4)>; /* I2C2_SCL */
173173
};
174174

175175
i2c3_pins: i2c3 {
176-
pinmux = <RZG2L_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */
177-
<RZG2L_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */
176+
pinmux = <RZV2H_PORT_PINMUX(3, 6, 1)>, /* I2C3_SDA */
177+
<RZV2H_PORT_PINMUX(3, 7, 1)>; /* I2C3_SCL */
178178
};
179179

180180
i2c6_pins: i2c6 {
181-
pinmux = <RZG2L_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */
182-
<RZG2L_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */
181+
pinmux = <RZV2H_PORT_PINMUX(4, 4, 1)>, /* I2C6_SDA */
182+
<RZV2H_PORT_PINMUX(4, 5, 1)>; /* I2C6_SCL */
183183
};
184184

185185
i2c7_pins: i2c7 {
186-
pinmux = <RZG2L_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */
187-
<RZG2L_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */
186+
pinmux = <RZV2H_PORT_PINMUX(4, 6, 1)>, /* I2C7_SDA */
187+
<RZV2H_PORT_PINMUX(4, 7, 1)>; /* I2C7_SCL */
188188
};
189189

190190
i2c8_pins: i2c8 {
191-
pinmux = <RZG2L_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */
192-
<RZG2L_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
191+
pinmux = <RZV2H_PORT_PINMUX(0, 6, 1)>, /* I2C8_SDA */
192+
<RZV2H_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
193193
};
194194

195195
scif_pins: scif {
@@ -199,7 +199,7 @@
199199

200200
sd1-pwr-en-hog {
201201
gpio-hog;
202-
gpios = <RZG2L_GPIO(10, 3) GPIO_ACTIVE_HIGH>;
202+
gpios = <RZV2H_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
203203
output-high;
204204
line-name = "sd1_pwr_en";
205205
};
@@ -219,7 +219,7 @@
219219
};
220220

221221
sd1_cd {
222-
pinmux = <RZG2L_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
222+
pinmux = <RZV2H_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
223223
};
224224
};
225225
};

‎arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@
2121
bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
2222
clock-lanes = <0>;
2323
data-lanes = <1 2 3>;
24+
line-orders = <0 3 0>;
2425
remote-endpoint = <&max96712_out0>;
2526
};
2627
};
@@ -41,6 +42,7 @@
4142
bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
4243
clock-lanes = <0>;
4344
data-lanes = <1 2 3>;
45+
line-orders = <0 3 0>;
4446
remote-endpoint = <&max96712_out1>;
4547
};
4648
};

‎include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2+
/*
3+
* This header provides constants for Renesas RZ/G3E family pinctrl bindings.
4+
*
5+
* Copyright (C) 2024 Renesas Electronics Corp.
6+
*
7+
*/
8+
9+
#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__
10+
#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__
11+
12+
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
13+
14+
/* RZG3E_Px = Offset address of PFC_P_mn - 0x20 */
15+
#define RZG3E_P0 0
16+
#define RZG3E_P1 1
17+
#define RZG3E_P2 2
18+
#define RZG3E_P3 3
19+
#define RZG3E_P4 4
20+
#define RZG3E_P5 5
21+
#define RZG3E_P6 6
22+
#define RZG3E_P7 7
23+
#define RZG3E_P8 8
24+
#define RZG3E_PA 10
25+
#define RZG3E_PB 11
26+
#define RZG3E_PC 12
27+
#define RZG3E_PD 13
28+
#define RZG3E_PE 14
29+
#define RZG3E_PF 15
30+
#define RZG3E_PG 16
31+
#define RZG3E_PH 17
32+
#define RZG3E_PJ 19
33+
#define RZG3E_PK 20
34+
#define RZG3E_PL 21
35+
#define RZG3E_PM 22
36+
#define RZG3E_PS 28
37+
38+
#define RZG3E_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3E_P##b, p, f)
39+
#define RZG3E_GPIO(port, pin) RZG2L_GPIO(RZG3E_P##port, pin)
40+
41+
#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__ */

‎include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,31 @@
1+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2+
/*
3+
* This header provides constants for Renesas RZ/V2H family pinctrl bindings.
4+
*
5+
* Copyright (C) 2024 Renesas Electronics Corp.
6+
*
7+
*/
8+
9+
#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__
10+
#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__
11+
12+
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
13+
14+
/* RZV2H_Px = Offset address of PFC_P_mn - 0x20 */
15+
#define RZV2H_P0 0
16+
#define RZV2H_P1 1
17+
#define RZV2H_P2 2
18+
#define RZV2H_P3 3
19+
#define RZV2H_P4 4
20+
#define RZV2H_P5 5
21+
#define RZV2H_P6 6
22+
#define RZV2H_P7 7
23+
#define RZV2H_P8 8
24+
#define RZV2H_P9 9
25+
#define RZV2H_PA 10
26+
#define RZV2H_PB 11
27+
28+
#define RZV2H_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZV2H_P##b, p, f)
29+
#define RZV2H_GPIO(port, pin) RZG2L_GPIO(RZV2H_P##port, pin)
30+
31+
#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__ */

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