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wenmliuandersson
wenmliu
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andersson
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arm64: dts: qcom: sm8550: Add support for camss
Add support for the camera subsystem on the SM8550 Qualcomm SoC. This includes bringing up the CSIPHY, CSID, VFE/RDI interfaces. SM8550 provides - 3 x VFE, 3 RDI per VFE - 2 x VFE Lite, 4 RDI per VFE - 3 x CSID - 2 x CSID Lite - 8 x CSI PHY Co-developed-by: Depeng Shao <quic_depengs@quicinc.com> Signed-off-by: Depeng Shao <quic_depengs@quicinc.com> Signed-off-by: Wenmeng Liu <quic_wenmliu@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20250612-sm8550-camss-v2-1-ed370124075e@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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‎arch/arm64/boot/dts/qcom/sm8550.dtsi‎

Lines changed: 210 additions & 0 deletions
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34063406
};
34073407
};
34083408

3409+
camss: isp@acb7000 {
3410+
compatible = "qcom,sm8550-camss";
3411+
3412+
reg = <0x0 0x0acb7000 0x0 0x0d00>,
3413+
<0x0 0x0acb9000 0x0 0x0d00>,
3414+
<0x0 0x0acbb000 0x0 0x0d00>,
3415+
<0x0 0x0acca000 0x0 0x0a00>,
3416+
<0x0 0x0acce000 0x0 0x0a00>,
3417+
<0x0 0x0acb6000 0x0 0x1000>,
3418+
<0x0 0x0ace4000 0x0 0x2000>,
3419+
<0x0 0x0ace6000 0x0 0x2000>,
3420+
<0x0 0x0ace8000 0x0 0x2000>,
3421+
<0x0 0x0acea000 0x0 0x2000>,
3422+
<0x0 0x0acec000 0x0 0x2000>,
3423+
<0x0 0x0acee000 0x0 0x2000>,
3424+
<0x0 0x0acf0000 0x0 0x2000>,
3425+
<0x0 0x0acf2000 0x0 0x2000>,
3426+
<0x0 0x0ac62000 0x0 0xf000>,
3427+
<0x0 0x0ac71000 0x0 0xf000>,
3428+
<0x0 0x0ac80000 0x0 0xf000>,
3429+
<0x0 0x0accb000 0x0 0x1800>,
3430+
<0x0 0x0accf000 0x0 0x1800>;
3431+
reg-names = "csid0",
3432+
"csid1",
3433+
"csid2",
3434+
"csid_lite0",
3435+
"csid_lite1",
3436+
"csid_wrapper",
3437+
"csiphy0",
3438+
"csiphy1",
3439+
"csiphy2",
3440+
"csiphy3",
3441+
"csiphy4",
3442+
"csiphy5",
3443+
"csiphy6",
3444+
"csiphy7",
3445+
"vfe0",
3446+
"vfe1",
3447+
"vfe2",
3448+
"vfe_lite0",
3449+
"vfe_lite1";
3450+
3451+
clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3452+
<&camcc CAM_CC_CPAS_AHB_CLK>,
3453+
<&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
3454+
<&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
3455+
<&camcc CAM_CC_CPAS_IFE_0_CLK>,
3456+
<&camcc CAM_CC_CPAS_IFE_1_CLK>,
3457+
<&camcc CAM_CC_CPAS_IFE_2_CLK>,
3458+
<&camcc CAM_CC_CSID_CLK>,
3459+
<&camcc CAM_CC_CSIPHY0_CLK>,
3460+
<&camcc CAM_CC_CSI0PHYTIMER_CLK>,
3461+
<&camcc CAM_CC_CSIPHY1_CLK>,
3462+
<&camcc CAM_CC_CSI1PHYTIMER_CLK>,
3463+
<&camcc CAM_CC_CSIPHY2_CLK>,
3464+
<&camcc CAM_CC_CSI2PHYTIMER_CLK>,
3465+
<&camcc CAM_CC_CSIPHY3_CLK>,
3466+
<&camcc CAM_CC_CSI3PHYTIMER_CLK>,
3467+
<&camcc CAM_CC_CSIPHY4_CLK>,
3468+
<&camcc CAM_CC_CSI4PHYTIMER_CLK>,
3469+
<&camcc CAM_CC_CSIPHY5_CLK>,
3470+
<&camcc CAM_CC_CSI5PHYTIMER_CLK>,
3471+
<&camcc CAM_CC_CSIPHY6_CLK>,
3472+
<&camcc CAM_CC_CSI6PHYTIMER_CLK>,
3473+
<&camcc CAM_CC_CSIPHY7_CLK>,
3474+
<&camcc CAM_CC_CSI7PHYTIMER_CLK>,
3475+
<&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
3476+
<&gcc GCC_CAMERA_HF_AXI_CLK>,
3477+
<&camcc CAM_CC_IFE_0_CLK>,
3478+
<&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
3479+
<&camcc CAM_CC_IFE_1_CLK>,
3480+
<&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
3481+
<&camcc CAM_CC_IFE_2_CLK>,
3482+
<&camcc CAM_CC_IFE_2_FAST_AHB_CLK>,
3483+
<&camcc CAM_CC_IFE_LITE_CLK>,
3484+
<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
3485+
<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
3486+
<&camcc CAM_CC_IFE_LITE_CSID_CLK>;
3487+
clock-names = "camnoc_axi",
3488+
"cpas_ahb",
3489+
"cpas_fast_ahb_clk",
3490+
"cpas_ife_lite",
3491+
"cpas_vfe0",
3492+
"cpas_vfe1",
3493+
"cpas_vfe2",
3494+
"csid",
3495+
"csiphy0",
3496+
"csiphy0_timer",
3497+
"csiphy1",
3498+
"csiphy1_timer",
3499+
"csiphy2",
3500+
"csiphy2_timer",
3501+
"csiphy3",
3502+
"csiphy3_timer",
3503+
"csiphy4",
3504+
"csiphy4_timer",
3505+
"csiphy5",
3506+
"csiphy5_timer",
3507+
"csiphy6",
3508+
"csiphy6_timer",
3509+
"csiphy7",
3510+
"csiphy7_timer",
3511+
"csiphy_rx",
3512+
"gcc_axi_hf",
3513+
"vfe0",
3514+
"vfe0_fast_ahb",
3515+
"vfe1",
3516+
"vfe1_fast_ahb",
3517+
"vfe2",
3518+
"vfe2_fast_ahb",
3519+
"vfe_lite",
3520+
"vfe_lite_ahb",
3521+
"vfe_lite_cphy_rx",
3522+
"vfe_lite_csid";
3523+
3524+
interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
3525+
<GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
3526+
<GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
3527+
<GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
3528+
<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
3529+
<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
3530+
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
3531+
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
3532+
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
3533+
<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
3534+
<GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
3535+
<GIC_SPI 278 IRQ_TYPE_EDGE_RISING>,
3536+
<GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
3537+
<GIC_SPI 602 IRQ_TYPE_EDGE_RISING>,
3538+
<GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
3539+
<GIC_SPI 688 IRQ_TYPE_EDGE_RISING>,
3540+
<GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
3541+
<GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
3542+
interrupt-names = "csid0",
3543+
"csid1",
3544+
"csid2",
3545+
"csid_lite0",
3546+
"csid_lite1",
3547+
"csiphy0",
3548+
"csiphy1",
3549+
"csiphy2",
3550+
"csiphy3",
3551+
"csiphy4",
3552+
"csiphy5",
3553+
"csiphy6",
3554+
"csiphy7",
3555+
"vfe0",
3556+
"vfe1",
3557+
"vfe2",
3558+
"vfe_lite0",
3559+
"vfe_lite1";
3560+
3561+
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
3562+
&config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
3563+
<&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
3564+
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
3565+
interconnect-names = "ahb",
3566+
"hf_0_mnoc";
3567+
3568+
iommus = <&apps_smmu 0x800 0x20>;
3569+
3570+
power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
3571+
<&camcc CAM_CC_IFE_1_GDSC>,
3572+
<&camcc CAM_CC_IFE_2_GDSC>,
3573+
<&camcc CAM_CC_TITAN_TOP_GDSC>;
3574+
power-domain-names = "ife0",
3575+
"ife1",
3576+
"ife2",
3577+
"top";
3578+
3579+
status = "disabled";
3580+
3581+
ports {
3582+
#address-cells = <1>;
3583+
#size-cells = <0>;
3584+
3585+
port@0 {
3586+
reg = <0>;
3587+
};
3588+
3589+
port@1 {
3590+
reg = <1>;
3591+
};
3592+
3593+
port@2 {
3594+
reg = <2>;
3595+
};
3596+
3597+
port@3 {
3598+
reg = <3>;
3599+
};
3600+
3601+
port@4 {
3602+
reg = <4>;
3603+
};
3604+
3605+
port@5 {
3606+
reg = <5>;
3607+
};
3608+
3609+
port@6 {
3610+
reg = <6>;
3611+
};
3612+
3613+
port@7 {
3614+
reg = <7>;
3615+
};
3616+
};
3617+
};
3618+
34093619
camcc: clock-controller@ade0000 {
34103620
compatible = "qcom,sm8550-camcc";
34113621
reg = <0 0x0ade0000 0 0x20000>;

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