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vijaysundarsherbertx
vijaysundars
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crypto: qat - enable telemetry for GEN6 devices
Enable telemetry for QAT GEN6 devices by defining the firmware data structures layouts, implementing the counters parsing logic and setting the required properties on the adf_tl_hw_data data structure. As for QAT GEN4, telemetry counters are exposed via debugfs using the interface described in Documentation/ABI/testing/debugfs-driver-qat_telemetry. Co-developed-by: George Abraham P <george.abraham.p@intel.com> Signed-off-by: George Abraham P <george.abraham.p@intel.com> Signed-off-by: Vijay Sundar Selvamani <vijay.sundar.selvamani@intel.com> Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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‎drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c‎

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@@ -19,6 +19,7 @@
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#include <adf_gen6_pm.h>
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#include <adf_gen6_ras.h>
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#include <adf_gen6_shared.h>
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#include <adf_gen6_tl.h>
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#include <adf_timer.h>
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#include "adf_6xxx_hw_data.h"
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#include "icp_qat_fw_comp.h"
@@ -861,12 +862,14 @@ void adf_init_hw_data_6xxx(struct adf_hw_device_data *hw_data)
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hw_data->init_device = adf_init_device;
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hw_data->enable_pm = enable_pm;
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hw_data->services_supported = services_supported;
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hw_data->num_rps = ADF_GEN6_ETR_MAX_BANKS;
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865867
adf_gen6_init_hw_csr_ops(&hw_data->csr_ops);
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adf_gen6_init_pf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen6_init_dc_ops(&hw_data->dc_ops);
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adf_gen6_init_vf_mig_ops(&hw_data->vfmig_ops);
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adf_gen6_init_ras_ops(&hw_data->ras_ops);
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adf_gen6_init_tl_data(&hw_data->tl_data);
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}
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void adf_clean_hw_data_6xxx(struct adf_hw_device_data *hw_data)

‎drivers/crypto/intel/qat/qat_common/Makefile‎

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@@ -50,6 +50,7 @@ intel_qat-$(CONFIG_DEBUG_FS) += adf_cnv_dbgfs.o \
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adf_gen4_pm_debugfs.o \
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adf_gen4_tl.o \
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adf_gen6_pm_dbgfs.o \
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adf_gen6_tl.o \
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adf_heartbeat_dbgfs.o \
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adf_heartbeat.o \
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adf_pm_dbgfs.o \

‎drivers/crypto/intel/qat/qat_common/adf_gen6_tl.c‎

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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2025 Intel Corporation. */
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#include <linux/export.h>
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#include "adf_gen6_tl.h"
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#include "adf_telemetry.h"
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#include "adf_tl_debugfs.h"
8+
#include "icp_qat_fw_init_admin.h"
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#define ADF_GEN6_TL_DEV_REG_OFF(reg) ADF_TL_DEV_REG_OFF(reg, gen6)
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#define ADF_GEN6_TL_RP_REG_OFF(reg) ADF_TL_RP_REG_OFF(reg, gen6)
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#define ADF_GEN6_TL_SL_UTIL_COUNTER(_name) \
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ADF_TL_COUNTER("util_" #_name, ADF_TL_SIMPLE_COUNT, \
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ADF_TL_SLICE_REG_OFF(_name, reg_tm_slice_util, gen6))
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#define ADF_GEN6_TL_SL_EXEC_COUNTER(_name) \
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ADF_TL_COUNTER("exec_" #_name, ADF_TL_SIMPLE_COUNT, \
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ADF_TL_SLICE_REG_OFF(_name, reg_tm_slice_exec_cnt, gen6))
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#define SLICE_IDX(sl) offsetof(struct icp_qat_fw_init_admin_slice_cnt, sl##_cnt)
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/* Device level counters. */
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static const struct adf_tl_dbg_counter dev_counters[] = {
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/* PCIe partial transactions. */
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ADF_TL_COUNTER(PCI_TRANS_CNT_NAME, ADF_TL_SIMPLE_COUNT,
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ADF_GEN6_TL_DEV_REG_OFF(reg_tl_prt_trans_cnt)),
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/* Max read latency[ns]. */
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ADF_TL_COUNTER(MAX_RD_LAT_NAME, ADF_TL_COUNTER_NS,
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ADF_GEN6_TL_DEV_REG_OFF(reg_tl_rd_lat_max)),
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/* Read latency average[ns]. */
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ADF_TL_COUNTER_LATENCY(RD_LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,
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ADF_GEN6_TL_DEV_REG_OFF(reg_tl_rd_lat_acc),
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ADF_GEN6_TL_DEV_REG_OFF(reg_tl_rd_cmpl_cnt)),
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/* Max "get to put" latency[ns]. */
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ADF_TL_COUNTER(MAX_LAT_NAME, ADF_TL_COUNTER_NS,
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ADF_GEN6_TL_DEV_REG_OFF(reg_tl_gp_lat_max)),
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/* "Get to put" latency average[ns]. */
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ADF_TL_COUNTER_LATENCY(LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,
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ADF_GEN6_TL_DEV_REG_OFF(reg_tl_gp_lat_acc),
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ADF_GEN6_TL_DEV_REG_OFF(reg_tl_ae_put_cnt)),
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/* PCIe write bandwidth[Mbps]. */
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ADF_TL_COUNTER(BW_IN_NAME, ADF_TL_COUNTER_MBPS,
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ADF_GEN6_TL_DEV_REG_OFF(reg_tl_bw_in)),
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/* PCIe read bandwidth[Mbps]. */
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ADF_TL_COUNTER(BW_OUT_NAME, ADF_TL_COUNTER_MBPS,
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ADF_GEN6_TL_DEV_REG_OFF(reg_tl_bw_out)),
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/* Page request latency average[ns]. */
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ADF_TL_COUNTER_LATENCY(PAGE_REQ_LAT_NAME, ADF_TL_COUNTER_NS_AVG,
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ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_page_req_lat_acc),
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ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_page_req_cnt)),
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/* Page translation latency average[ns]. */
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ADF_TL_COUNTER_LATENCY(AT_TRANS_LAT_NAME, ADF_TL_COUNTER_NS_AVG,
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ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_trans_lat_acc),
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ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_trans_lat_cnt)),
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/* Maximum uTLB used. */
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ADF_TL_COUNTER(AT_MAX_UTLB_USED_NAME, ADF_TL_SIMPLE_COUNT,
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ADF_GEN6_TL_DEV_REG_OFF(reg_tl_at_max_utlb_used)),
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};
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/* Accelerator utilization counters */
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static const struct adf_tl_dbg_counter sl_util_counters[ADF_TL_SL_CNT_COUNT] = {
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/* Compression accelerator utilization. */
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[SLICE_IDX(cpr)] = ADF_GEN6_TL_SL_UTIL_COUNTER(cnv),
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/* Decompression accelerator utilization. */
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[SLICE_IDX(dcpr)] = ADF_GEN6_TL_SL_UTIL_COUNTER(dcprz),
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/* PKE accelerator utilization. */
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[SLICE_IDX(pke)] = ADF_GEN6_TL_SL_UTIL_COUNTER(pke),
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/* Wireless Authentication accelerator utilization. */
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[SLICE_IDX(wat)] = ADF_GEN6_TL_SL_UTIL_COUNTER(wat),
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/* Wireless Cipher accelerator utilization. */
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[SLICE_IDX(wcp)] = ADF_GEN6_TL_SL_UTIL_COUNTER(wcp),
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/* UCS accelerator utilization. */
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[SLICE_IDX(ucs)] = ADF_GEN6_TL_SL_UTIL_COUNTER(ucs),
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/* Authentication accelerator utilization. */
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[SLICE_IDX(ath)] = ADF_GEN6_TL_SL_UTIL_COUNTER(ath),
78+
};
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/* Accelerator execution counters */
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static const struct adf_tl_dbg_counter sl_exec_counters[ADF_TL_SL_CNT_COUNT] = {
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/* Compression accelerator execution count. */
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[SLICE_IDX(cpr)] = ADF_GEN6_TL_SL_EXEC_COUNTER(cnv),
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/* Decompression accelerator execution count. */
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[SLICE_IDX(dcpr)] = ADF_GEN6_TL_SL_EXEC_COUNTER(dcprz),
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/* PKE execution count. */
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[SLICE_IDX(pke)] = ADF_GEN6_TL_SL_EXEC_COUNTER(pke),
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/* Wireless Authentication accelerator execution count. */
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[SLICE_IDX(wat)] = ADF_GEN6_TL_SL_EXEC_COUNTER(wat),
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/* Wireless Cipher accelerator execution count. */
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[SLICE_IDX(wcp)] = ADF_GEN6_TL_SL_EXEC_COUNTER(wcp),
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/* UCS accelerator execution count. */
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[SLICE_IDX(ucs)] = ADF_GEN6_TL_SL_EXEC_COUNTER(ucs),
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/* Authentication accelerator execution count. */
95+
[SLICE_IDX(ath)] = ADF_GEN6_TL_SL_EXEC_COUNTER(ath),
96+
};
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/* Ring pair counters. */
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static const struct adf_tl_dbg_counter rp_counters[] = {
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/* PCIe partial transactions. */
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ADF_TL_COUNTER(PCI_TRANS_CNT_NAME, ADF_TL_SIMPLE_COUNT,
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ADF_GEN6_TL_RP_REG_OFF(reg_tl_prt_trans_cnt)),
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/* "Get to put" latency average[ns]. */
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ADF_TL_COUNTER_LATENCY(LAT_ACC_NAME, ADF_TL_COUNTER_NS_AVG,
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ADF_GEN6_TL_RP_REG_OFF(reg_tl_gp_lat_acc),
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ADF_GEN6_TL_RP_REG_OFF(reg_tl_ae_put_cnt)),
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/* PCIe write bandwidth[Mbps]. */
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ADF_TL_COUNTER(BW_IN_NAME, ADF_TL_COUNTER_MBPS,
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ADF_GEN6_TL_RP_REG_OFF(reg_tl_bw_in)),
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/* PCIe read bandwidth[Mbps]. */
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ADF_TL_COUNTER(BW_OUT_NAME, ADF_TL_COUNTER_MBPS,
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ADF_GEN6_TL_RP_REG_OFF(reg_tl_bw_out)),
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/* Message descriptor DevTLB hit rate. */
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ADF_TL_COUNTER(AT_GLOB_DTLB_HIT_NAME, ADF_TL_SIMPLE_COUNT,
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ADF_GEN6_TL_RP_REG_OFF(reg_tl_at_glob_devtlb_hit)),
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/* Message descriptor DevTLB miss rate. */
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ADF_TL_COUNTER(AT_GLOB_DTLB_MISS_NAME, ADF_TL_SIMPLE_COUNT,
118+
ADF_GEN6_TL_RP_REG_OFF(reg_tl_at_glob_devtlb_miss)),
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/* Payload DevTLB hit rate. */
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ADF_TL_COUNTER(AT_PAYLD_DTLB_HIT_NAME, ADF_TL_SIMPLE_COUNT,
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ADF_GEN6_TL_RP_REG_OFF(reg_tl_at_payld_devtlb_hit)),
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/* Payload DevTLB miss rate. */
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ADF_TL_COUNTER(AT_PAYLD_DTLB_MISS_NAME, ADF_TL_SIMPLE_COUNT,
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ADF_GEN6_TL_RP_REG_OFF(reg_tl_at_payld_devtlb_miss)),
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};
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void adf_gen6_init_tl_data(struct adf_tl_hw_data *tl_data)
128+
{
129+
tl_data->layout_sz = ADF_GEN6_TL_LAYOUT_SZ;
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tl_data->slice_reg_sz = ADF_GEN6_TL_SLICE_REG_SZ;
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tl_data->rp_reg_sz = ADF_GEN6_TL_RP_REG_SZ;
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tl_data->num_hbuff = ADF_GEN6_TL_NUM_HIST_BUFFS;
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tl_data->max_rp = ADF_GEN6_TL_MAX_RP_NUM;
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tl_data->msg_cnt_off = ADF_GEN6_TL_MSG_CNT_OFF;
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tl_data->cpp_ns_per_cycle = ADF_GEN6_CPP_NS_PER_CYCLE;
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tl_data->bw_units_to_bytes = ADF_GEN6_TL_BW_HW_UNITS_TO_BYTES;
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138+
tl_data->dev_counters = dev_counters;
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tl_data->num_dev_counters = ARRAY_SIZE(dev_counters);
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tl_data->sl_util_counters = sl_util_counters;
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tl_data->sl_exec_counters = sl_exec_counters;
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tl_data->rp_counters = rp_counters;
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tl_data->num_rp_counters = ARRAY_SIZE(rp_counters);
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tl_data->max_sl_cnt = ADF_GEN6_TL_MAX_SLICES_PER_TYPE;
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}
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EXPORT_SYMBOL_GPL(adf_gen6_init_tl_data);

‎drivers/crypto/intel/qat/qat_common/adf_gen6_tl.h‎

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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2025 Intel Corporation. */
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#ifndef ADF_GEN6_TL_H
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#define ADF_GEN6_TL_H
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#include <linux/types.h>
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struct adf_tl_hw_data;
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/* Computation constants. */
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#define ADF_GEN6_CPP_NS_PER_CYCLE 2
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#define ADF_GEN6_TL_BW_HW_UNITS_TO_BYTES 64
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/* Maximum aggregation time. Value is in milliseconds. */
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#define ADF_GEN6_TL_MAX_AGGR_TIME_MS 4000
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/* Number of buffers to store historic values. */
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#define ADF_GEN6_TL_NUM_HIST_BUFFS \
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(ADF_GEN6_TL_MAX_AGGR_TIME_MS / ADF_TL_DATA_WR_INTERVAL_MS)
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/* Max number of HW resources of one type */
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#define ADF_GEN6_TL_MAX_SLICES_PER_TYPE 32
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#define MAX_ATH_SL_COUNT 7
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#define MAX_CNV_SL_COUNT 2
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#define MAX_DCPRZ_SL_COUNT 2
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#define MAX_PKE_SL_COUNT 32
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#define MAX_UCS_SL_COUNT 4
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#define MAX_WAT_SL_COUNT 5
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#define MAX_WCP_SL_COUNT 5
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#define MAX_ATH_CMDQ_COUNT 14
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#define MAX_CNV_CMDQ_COUNT 6
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#define MAX_DCPRZ_CMDQ_COUNT 6
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#define MAX_PKE_CMDQ_COUNT 32
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#define MAX_UCS_CMDQ_COUNT 12
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#define MAX_WAT_CMDQ_COUNT 35
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#define MAX_WCP_CMDQ_COUNT 35
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/* Max number of simultaneously monitored ring pairs. */
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#define ADF_GEN6_TL_MAX_RP_NUM 4
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/**
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* struct adf_gen6_tl_slice_data_regs - HW slice data as populated by FW.
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* @reg_tm_slice_exec_cnt: Slice execution count.
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* @reg_tm_slice_util: Slice utilization.
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*/
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struct adf_gen6_tl_slice_data_regs {
47+
__u32 reg_tm_slice_exec_cnt;
48+
__u32 reg_tm_slice_util;
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};
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#define ADF_GEN6_TL_SLICE_REG_SZ sizeof(struct adf_gen6_tl_slice_data_regs)
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/**
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* struct adf_gen6_tl_cmdq_data_regs - HW CMDQ data as populated by FW.
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* @reg_tm_cmdq_wait_cnt: CMDQ wait count.
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* @reg_tm_cmdq_exec_cnt: CMDQ execution count.
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* @reg_tm_cmdq_drain_cnt: CMDQ drain count.
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*/
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struct adf_gen6_tl_cmdq_data_regs {
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__u32 reg_tm_cmdq_wait_cnt;
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__u32 reg_tm_cmdq_exec_cnt;
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__u32 reg_tm_cmdq_drain_cnt;
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__u32 reserved;
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};
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#define ADF_GEN6_TL_CMDQ_REG_SZ sizeof(struct adf_gen6_tl_cmdq_data_regs)
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/**
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* struct adf_gen6_tl_device_data_regs - This structure stores device telemetry
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* counter values as are being populated periodically by device.
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* @reg_tl_rd_lat_acc: read latency accumulator
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* @reg_tl_gp_lat_acc: "get to put" latency accumulator
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* @reg_tl_at_page_req_lat_acc: AT/DevTLB page request latency accumulator
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* @reg_tl_at_trans_lat_acc: DevTLB transaction latency accumulator
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* @reg_tl_re_acc: accumulated ring empty time
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* @reg_tl_prt_trans_cnt: PCIe partial transactions
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* @reg_tl_rd_lat_max: maximum logged read latency
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* @reg_tl_rd_cmpl_cnt: read requests completed count
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* @reg_tl_gp_lat_max: maximum logged get to put latency
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* @reg_tl_ae_put_cnt: Accelerator Engine put counts across all rings
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* @reg_tl_bw_in: PCIe write bandwidth
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* @reg_tl_bw_out: PCIe read bandwidth
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* @reg_tl_at_page_req_cnt: DevTLB page requests count
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* @reg_tl_at_trans_lat_cnt: DevTLB transaction latency samples count
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* @reg_tl_at_max_utlb_used: maximum uTLB used
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* @reg_tl_re_cnt: ring empty time samples count
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* @reserved: reserved
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* @ath_slices: array of Authentication slices utilization registers
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* @cnv_slices: array of Compression slices utilization registers
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* @dcprz_slices: array of Decompression slices utilization registers
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* @pke_slices: array of PKE slices utilization registers
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* @ucs_slices: array of UCS slices utilization registers
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* @wat_slices: array of Wireless Authentication slices utilization registers
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* @wcp_slices: array of Wireless Cipher slices utilization registers
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* @ath_cmdq: array of Authentication cmdq telemetry registers
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* @cnv_cmdq: array of Compression cmdq telemetry registers
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* @dcprz_cmdq: array of Decomopression cmdq telemetry registers
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* @pke_cmdq: array of PKE cmdq telemetry registers
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* @ucs_cmdq: array of UCS cmdq telemetry registers
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* @wat_cmdq: array of Wireless Authentication cmdq telemetry registers
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* @wcp_cmdq: array of Wireless Cipher cmdq telemetry registers
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*/
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struct adf_gen6_tl_device_data_regs {
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__u64 reg_tl_rd_lat_acc;
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__u64 reg_tl_gp_lat_acc;
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__u64 reg_tl_at_page_req_lat_acc;
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__u64 reg_tl_at_trans_lat_acc;
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__u64 reg_tl_re_acc;
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__u32 reg_tl_prt_trans_cnt;
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__u32 reg_tl_rd_lat_max;
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__u32 reg_tl_rd_cmpl_cnt;
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__u32 reg_tl_gp_lat_max;
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__u32 reg_tl_ae_put_cnt;
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__u32 reg_tl_bw_in;
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__u32 reg_tl_bw_out;
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__u32 reg_tl_at_page_req_cnt;
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__u32 reg_tl_at_trans_lat_cnt;
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__u32 reg_tl_at_max_utlb_used;
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__u32 reg_tl_re_cnt;
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__u32 reserved;
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struct adf_gen6_tl_slice_data_regs ath_slices[MAX_ATH_SL_COUNT];
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struct adf_gen6_tl_slice_data_regs cnv_slices[MAX_CNV_SL_COUNT];
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struct adf_gen6_tl_slice_data_regs dcprz_slices[MAX_DCPRZ_SL_COUNT];
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struct adf_gen6_tl_slice_data_regs pke_slices[MAX_PKE_SL_COUNT];
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struct adf_gen6_tl_slice_data_regs ucs_slices[MAX_UCS_SL_COUNT];
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struct adf_gen6_tl_slice_data_regs wat_slices[MAX_WAT_SL_COUNT];
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struct adf_gen6_tl_slice_data_regs wcp_slices[MAX_WCP_SL_COUNT];
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struct adf_gen6_tl_cmdq_data_regs ath_cmdq[MAX_ATH_CMDQ_COUNT];
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struct adf_gen6_tl_cmdq_data_regs cnv_cmdq[MAX_CNV_CMDQ_COUNT];
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struct adf_gen6_tl_cmdq_data_regs dcprz_cmdq[MAX_DCPRZ_CMDQ_COUNT];
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struct adf_gen6_tl_cmdq_data_regs pke_cmdq[MAX_PKE_CMDQ_COUNT];
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struct adf_gen6_tl_cmdq_data_regs ucs_cmdq[MAX_UCS_CMDQ_COUNT];
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struct adf_gen6_tl_cmdq_data_regs wat_cmdq[MAX_WAT_CMDQ_COUNT];
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struct adf_gen6_tl_cmdq_data_regs wcp_cmdq[MAX_WCP_CMDQ_COUNT];
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};
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/**
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* struct adf_gen6_tl_ring_pair_data_regs - This structure stores ring pair
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* telemetry counter values as they are being populated periodically by device.
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* @reg_tl_gp_lat_acc: get-put latency accumulator
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* @reg_tl_re_acc: accumulated ring empty time
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* @reg_tl_pci_trans_cnt: PCIe partial transactions
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* @reg_tl_ae_put_cnt: Accelerator Engine put counts across all rings
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* @reg_tl_bw_in: PCIe write bandwidth
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* @reg_tl_bw_out: PCIe read bandwidth
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* @reg_tl_at_glob_devtlb_hit: Message descriptor DevTLB hit rate
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* @reg_tl_at_glob_devtlb_miss: Message descriptor DevTLB miss rate
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* @reg_tl_at_payld_devtlb_hit: Payload DevTLB hit rate
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* @reg_tl_at_payld_devtlb_miss: Payload DevTLB miss rate
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* @reg_tl_re_cnt: ring empty time samples count
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* @reserved1: reserved
152+
*/
153+
struct adf_gen6_tl_ring_pair_data_regs {
154+
__u64 reg_tl_gp_lat_acc;
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__u64 reg_tl_re_acc;
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__u32 reg_tl_prt_trans_cnt;
157+
__u32 reg_tl_ae_put_cnt;
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__u32 reg_tl_bw_in;
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__u32 reg_tl_bw_out;
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__u32 reg_tl_at_glob_devtlb_hit;
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__u32 reg_tl_at_glob_devtlb_miss;
162+
__u32 reg_tl_at_payld_devtlb_hit;
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__u32 reg_tl_at_payld_devtlb_miss;
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__u32 reg_tl_re_cnt;
165+
__u32 reserved1;
166+
};
167+
168+
#define ADF_GEN6_TL_RP_REG_SZ sizeof(struct adf_gen6_tl_ring_pair_data_regs)
169+
170+
/**
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* struct adf_gen6_tl_layout - This structure represents the entire telemetry
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* counters data: Device + 4 Ring Pairs as they are being populated periodically
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* by device.
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* @tl_device_data_regs: structure of device telemetry registers
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* @tl_ring_pairs_data_regs: array of ring pairs telemetry registers
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* @reg_tl_msg_cnt: telemetry message counter
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* @reserved: reserved
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*/
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struct adf_gen6_tl_layout {
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struct adf_gen6_tl_device_data_regs tl_device_data_regs;
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struct adf_gen6_tl_ring_pair_data_regs
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tl_ring_pairs_data_regs[ADF_GEN6_TL_MAX_RP_NUM];
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__u32 reg_tl_msg_cnt;
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__u32 reserved;
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};
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#define ADF_GEN6_TL_LAYOUT_SZ sizeof(struct adf_gen6_tl_layout)
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#define ADF_GEN6_TL_MSG_CNT_OFF \
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offsetof(struct adf_gen6_tl_layout, reg_tl_msg_cnt)
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#ifdef CONFIG_DEBUG_FS
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void adf_gen6_init_tl_data(struct adf_tl_hw_data *tl_data);
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#else
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static inline void adf_gen6_init_tl_data(struct adf_tl_hw_data *tl_data)
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{
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}
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#endif /* CONFIG_DEBUG_FS */
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#endif /* ADF_GEN6_TL_H */

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