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clk: mediatek: Add MT8196 pextpsys clock support
Add support for the MT8196 pextpsys clock controller, which provides clock gate control for PCIe. Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> # CLK_OPS_PARENT_ENABLE removal Signed-off-by: Laura Nao <laura.nao@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Lines changed: 139 additions & 0 deletions

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‎drivers/clk/mediatek/Kconfig‎

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@@ -1010,6 +1010,13 @@ config COMMON_CLK_MT8196
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help
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This driver supports MediaTek MT8196 basic clocks.
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config COMMON_CLK_MT8196_PEXTPSYS
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tristate "Clock driver for MediaTek MT8196 pextpsys"
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depends on COMMON_CLK_MT8196
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default COMMON_CLK_MT8196
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help
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This driver supports MediaTek MT8196 pextpsys clocks.
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config COMMON_CLK_MT8196_UFSSYS
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tristate "Clock driver for MediaTek MT8196 ufssys"
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depends on COMMON_CLK_MT8196

‎drivers/clk/mediatek/Makefile‎

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@@ -153,6 +153,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
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obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-topckgen.o \
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clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \
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clk-mt8196-peri_ao.o
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obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o
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obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o
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obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
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obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o

‎drivers/clk/mediatek/clk-mt8196-pextp.c‎

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2025 MediaTek Inc.
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* Guangjie Song <guangjie.song@mediatek.com>
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* Copyright (c) 2025 Collabora Ltd.
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* Laura Nao <laura.nao@collabora.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8196-clock.h>
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#include <dt-bindings/reset/mediatek,mt8196-resets.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include "reset.h"
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#define MT8196_PEXTP_RST0_SET_OFFSET 0x8
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static const struct mtk_gate_regs pext_cg_regs = {
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.set_ofs = 0x18,
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.clr_ofs = 0x1c,
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.sta_ofs = 0x14,
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};
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#define GATE_PEXT(_id, _name, _parent, _shift) {\
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &pext_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr,\
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}
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static const struct mtk_gate pext_clks[] = {
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GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_TL, "pext_pm0_tl", "tl", 0),
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GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_REF, "pext_pm0_ref", "clk26m", 1),
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GATE_PEXT(CLK_PEXT_PEXTP_PHY_P0_MCU_BUS, "pext_pp0_mcu_bus", "clk26m", 6),
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GATE_PEXT(CLK_PEXT_PEXTP_PHY_P0_PEXTP_REF, "pext_pp0_pextp_ref", "clk26m", 7),
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GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_AXI_250, "pext_pm0_axi_250", "ufs_pexpt0_mem_sub", 12),
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GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_AHB_APB, "pext_pm0_ahb_apb", "ufs_pextp0_axi", 13),
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GATE_PEXT(CLK_PEXT_PEXTP_MAC_P0_PL_P, "pext_pm0_pl_p", "clk26m", 14),
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GATE_PEXT(CLK_PEXT_PEXTP_VLP_AO_P0_LP, "pext_pextp_vlp_ao_p0_lp", "clk26m", 19),
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};
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static u16 pext_rst_ofs[] = { MT8196_PEXTP_RST0_SET_OFFSET };
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static u16 pext_rst_idx_map[] = {
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[MT8196_PEXTP0_RST0_PCIE0_MAC] = 0,
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[MT8196_PEXTP0_RST0_PCIE0_PHY] = 1,
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};
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static const struct mtk_clk_rst_desc pext_rst_desc = {
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.version = MTK_RST_SET_CLR,
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.rst_bank_ofs = pext_rst_ofs,
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.rst_bank_nr = ARRAY_SIZE(pext_rst_ofs),
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.rst_idx_map = pext_rst_idx_map,
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.rst_idx_map_nr = ARRAY_SIZE(pext_rst_idx_map),
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};
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static const struct mtk_clk_desc pext_mcd = {
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.clks = pext_clks,
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.num_clks = ARRAY_SIZE(pext_clks),
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.rst_desc = &pext_rst_desc,
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};
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static const struct mtk_gate pext1_clks[] = {
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GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_TL, "pext1_pm1_tl", "tl_p1", 0),
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GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_REF, "pext1_pm1_ref", "clk26m", 1),
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GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_TL, "pext1_pm2_tl", "tl_p2", 2),
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GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_REF, "pext1_pm2_ref", "clk26m", 3),
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GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P1_MCU_BUS, "pext1_pp1_mcu_bus", "clk26m", 8),
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GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P1_PEXTP_REF, "pext1_pp1_pextp_ref", "clk26m", 9),
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GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P2_MCU_BUS, "pext1_pp2_mcu_bus", "clk26m", 10),
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GATE_PEXT(CLK_PEXT1_PEXTP_PHY_P2_PEXTP_REF, "pext1_pp2_pextp_ref", "clk26m", 11),
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GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_AXI_250, "pext1_pm1_axi_250",
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"pextp1_usb_axi", 16),
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GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_AHB_APB, "pext1_pm1_ahb_apb",
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"pextp1_usb_mem_sub", 17),
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GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P1_PL_P, "pext1_pm1_pl_p", "clk26m", 18),
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GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_AXI_250, "pext1_pm2_axi_250",
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"pextp1_usb_axi", 19),
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GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_AHB_APB, "pext1_pm2_ahb_apb",
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"pextp1_usb_mem_sub", 20),
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GATE_PEXT(CLK_PEXT1_PEXTP_MAC_P2_PL_P, "pext1_pm2_pl_p", "clk26m", 21),
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GATE_PEXT(CLK_PEXT1_PEXTP_VLP_AO_P1_LP, "pext1_pextp_vlp_ao_p1_lp", "clk26m", 26),
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GATE_PEXT(CLK_PEXT1_PEXTP_VLP_AO_P2_LP, "pext1_pextp_vlp_ao_p2_lp", "clk26m", 27),
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};
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static u16 pext1_rst_idx_map[] = {
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[MT8196_PEXTP1_RST0_PCIE1_MAC] = 0,
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[MT8196_PEXTP1_RST0_PCIE1_PHY] = 1,
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[MT8196_PEXTP1_RST0_PCIE2_MAC] = 8,
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[MT8196_PEXTP1_RST0_PCIE2_PHY] = 9,
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};
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static const struct mtk_clk_rst_desc pext1_rst_desc = {
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.version = MTK_RST_SET_CLR,
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.rst_bank_ofs = pext_rst_ofs,
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.rst_bank_nr = ARRAY_SIZE(pext_rst_ofs),
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.rst_idx_map = pext1_rst_idx_map,
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.rst_idx_map_nr = ARRAY_SIZE(pext1_rst_idx_map),
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};
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static const struct mtk_clk_desc pext1_mcd = {
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.clks = pext1_clks,
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.num_clks = ARRAY_SIZE(pext1_clks),
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.rst_desc = &pext1_rst_desc,
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};
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static const struct of_device_id of_match_clk_mt8196_pextp[] = {
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{ .compatible = "mediatek,mt8196-pextp0cfg-ao", .data = &pext_mcd },
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{ .compatible = "mediatek,mt8196-pextp1cfg-ao", .data = &pext1_mcd },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_pextp);
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static struct platform_driver clk_mt8196_pextp_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8196-pextp",
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.of_match_table = of_match_clk_mt8196_pextp,
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},
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};
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module_platform_driver(clk_mt8196_pextp_drv);
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MODULE_DESCRIPTION("MediaTek MT8196 PCIe transmit phy clocks driver");
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MODULE_LICENSE("GPL");

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