Skip to content

Commit cd7d117

Browse files
author
Bartosz Golaszewski
committed
gpio: bcm-kona: use lock guards
Reduce the code complexity by using automatic lock guards with the raw spinlock. Link: https://lore.kernel.org/r/20250310-gpiochip-set-conversion-v1-1-03798bb833eb@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
1 parent 496fa74 commit cd7d117

1 file changed

Lines changed: 18 additions & 46 deletions

File tree

‎drivers/gpio/gpio-bcm-kona.c‎

Lines changed: 18 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
*/
88

99
#include <linux/bitops.h>
10+
#include <linux/cleanup.h>
1011
#include <linux/err.h>
1112
#include <linux/gpio/driver.h>
1213
#include <linux/init.h>
@@ -100,7 +101,6 @@ static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
100101
unsigned gpio)
101102
{
102103
u32 val;
103-
unsigned long flags;
104104
int bank_id = GPIO_BANK(gpio);
105105
int bit = GPIO_BIT(gpio);
106106
struct bcm_kona_gpio_bank *bank = &kona_gpio->banks[bank_id];
@@ -112,33 +112,28 @@ static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
112112
}
113113

114114
if (--bank->gpio_unlock_count[bit] == 0) {
115-
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
115+
guard(raw_spinlock_irqsave)(&kona_gpio->lock);
116116

117117
val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
118118
val |= BIT(bit);
119119
bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
120-
121-
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
122120
}
123121
}
124122

125123
static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
126124
unsigned gpio)
127125
{
128126
u32 val;
129-
unsigned long flags;
130127
int bank_id = GPIO_BANK(gpio);
131128
int bit = GPIO_BIT(gpio);
132129
struct bcm_kona_gpio_bank *bank = &kona_gpio->banks[bank_id];
133130

134131
if (bank->gpio_unlock_count[bit] == 0) {
135-
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
132+
guard(raw_spinlock_irqsave)(&kona_gpio->lock);
136133

137134
val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
138135
val &= ~BIT(bit);
139136
bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
140-
141-
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
142137
}
143138

144139
++bank->gpio_unlock_count[bit];
@@ -161,24 +156,21 @@ static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
161156
int bank_id = GPIO_BANK(gpio);
162157
int bit = GPIO_BIT(gpio);
163158
u32 val, reg_offset;
164-
unsigned long flags;
165159

166160
kona_gpio = gpiochip_get_data(chip);
167161
reg_base = kona_gpio->reg_base;
168-
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
162+
163+
guard(raw_spinlock_irqsave)(&kona_gpio->lock);
169164

170165
/* this function only applies to output pin */
171166
if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
172-
goto out;
167+
return;
173168

174169
reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
175170

176171
val = readl(reg_base + reg_offset);
177172
val |= BIT(bit);
178173
writel(val, reg_base + reg_offset);
179-
180-
out:
181-
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
182174
}
183175

184176
static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
@@ -188,11 +180,11 @@ static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
188180
int bank_id = GPIO_BANK(gpio);
189181
int bit = GPIO_BIT(gpio);
190182
u32 val, reg_offset;
191-
unsigned long flags;
192183

193184
kona_gpio = gpiochip_get_data(chip);
194185
reg_base = kona_gpio->reg_base;
195-
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
186+
187+
guard(raw_spinlock_irqsave)(&kona_gpio->lock);
196188

197189
if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
198190
reg_offset = GPIO_IN_STATUS(bank_id);
@@ -202,8 +194,6 @@ static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
202194
/* read the GPIO bank status */
203195
val = readl(reg_base + reg_offset);
204196

205-
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
206-
207197
/* return the specified bit status */
208198
return !!(val & BIT(bit));
209199
}
@@ -228,19 +218,17 @@ static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
228218
struct bcm_kona_gpio *kona_gpio;
229219
void __iomem *reg_base;
230220
u32 val;
231-
unsigned long flags;
232221

233222
kona_gpio = gpiochip_get_data(chip);
234223
reg_base = kona_gpio->reg_base;
235-
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
224+
225+
guard(raw_spinlock_irqsave)(&kona_gpio->lock);
236226

237227
val = readl(reg_base + GPIO_CONTROL(gpio));
238228
val &= ~GPIO_GPCTR0_IOTR_MASK;
239229
val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
240230
writel(val, reg_base + GPIO_CONTROL(gpio));
241231

242-
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
243-
244232
return 0;
245233
}
246234

@@ -252,11 +240,11 @@ static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
252240
int bank_id = GPIO_BANK(gpio);
253241
int bit = GPIO_BIT(gpio);
254242
u32 val, reg_offset;
255-
unsigned long flags;
256243

257244
kona_gpio = gpiochip_get_data(chip);
258245
reg_base = kona_gpio->reg_base;
259-
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
246+
247+
guard(raw_spinlock_irqsave)(&kona_gpio->lock);
260248

261249
val = readl(reg_base + GPIO_CONTROL(gpio));
262250
val &= ~GPIO_GPCTR0_IOTR_MASK;
@@ -268,8 +256,6 @@ static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
268256
val |= BIT(bit);
269257
writel(val, reg_base + reg_offset);
270258

271-
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
272-
273259
return 0;
274260
}
275261

@@ -289,7 +275,6 @@ static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
289275
struct bcm_kona_gpio *kona_gpio;
290276
void __iomem *reg_base;
291277
u32 val, res;
292-
unsigned long flags;
293278

294279
kona_gpio = gpiochip_get_data(chip);
295280
reg_base = kona_gpio->reg_base;
@@ -312,7 +297,7 @@ static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
312297
}
313298

314299
/* spin lock for read-modify-write of the GPIO register */
315-
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
300+
guard(raw_spinlock_irqsave)(&kona_gpio->lock);
316301

317302
val = readl(reg_base + GPIO_CONTROL(gpio));
318303
val &= ~GPIO_GPCTR0_DBR_MASK;
@@ -327,8 +312,6 @@ static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
327312

328313
writel(val, reg_base + GPIO_CONTROL(gpio));
329314

330-
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
331-
332315
return 0;
333316
}
334317

@@ -367,17 +350,15 @@ static void bcm_kona_gpio_irq_ack(struct irq_data *d)
367350
int bank_id = GPIO_BANK(gpio);
368351
int bit = GPIO_BIT(gpio);
369352
u32 val;
370-
unsigned long flags;
371353

372354
kona_gpio = irq_data_get_irq_chip_data(d);
373355
reg_base = kona_gpio->reg_base;
374-
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
356+
357+
guard(raw_spinlock_irqsave)(&kona_gpio->lock);
375358

376359
val = readl(reg_base + GPIO_INT_STATUS(bank_id));
377360
val |= BIT(bit);
378361
writel(val, reg_base + GPIO_INT_STATUS(bank_id));
379-
380-
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
381362
}
382363

383364
static void bcm_kona_gpio_irq_mask(struct irq_data *d)
@@ -388,19 +369,16 @@ static void bcm_kona_gpio_irq_mask(struct irq_data *d)
388369
int bank_id = GPIO_BANK(gpio);
389370
int bit = GPIO_BIT(gpio);
390371
u32 val;
391-
unsigned long flags;
392372

393373
kona_gpio = irq_data_get_irq_chip_data(d);
394374
reg_base = kona_gpio->reg_base;
395375

396-
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
376+
guard(raw_spinlock_irqsave)(&kona_gpio->lock);
397377

398378
val = readl(reg_base + GPIO_INT_MASK(bank_id));
399379
val |= BIT(bit);
400380
writel(val, reg_base + GPIO_INT_MASK(bank_id));
401381
gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio);
402-
403-
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
404382
}
405383

406384
static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
@@ -411,19 +389,16 @@ static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
411389
int bank_id = GPIO_BANK(gpio);
412390
int bit = GPIO_BIT(gpio);
413391
u32 val;
414-
unsigned long flags;
415392

416393
kona_gpio = irq_data_get_irq_chip_data(d);
417394
reg_base = kona_gpio->reg_base;
418395

419-
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
396+
guard(raw_spinlock_irqsave)(&kona_gpio->lock);
420397

421398
val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
422399
val |= BIT(bit);
423400
writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
424401
gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio);
425-
426-
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
427402
}
428403

429404
static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
@@ -433,7 +408,6 @@ static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
433408
unsigned gpio = d->hwirq;
434409
u32 lvl_type;
435410
u32 val;
436-
unsigned long flags;
437411

438412
kona_gpio = irq_data_get_irq_chip_data(d);
439413
reg_base = kona_gpio->reg_base;
@@ -459,15 +433,13 @@ static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
459433
return -EINVAL;
460434
}
461435

462-
raw_spin_lock_irqsave(&kona_gpio->lock, flags);
436+
guard(raw_spinlock_irqsave)(&kona_gpio->lock);
463437

464438
val = readl(reg_base + GPIO_CONTROL(gpio));
465439
val &= ~GPIO_GPCTR0_ITR_MASK;
466440
val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
467441
writel(val, reg_base + GPIO_CONTROL(gpio));
468442

469-
raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
470-
471443
return 0;
472444
}
473445

0 commit comments

Comments
 (0)