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Merge tag 'iommu-updates-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux
Pull iommu updates from Joerg Roedel: - Introduction of the generic IO page-table framework with support for Intel and AMD IOMMU formats from Jason. This has good potential for unifying more IO page-table implementations and making future enhancements more easy. But this also needed quite some fixes during development. All known issues have been fixed, but my feeling is that there is a higher potential than usual that more might be needed. - Intel VT-d updates: - Use right invalidation hint in qi_desc_iotlb() - Reduce the scope of INTEL_IOMMU_FLOPPY_WA - ARM-SMMU updates: - Qualcomm device-tree binding updates for Kaanapali and Glymur SoCs and a new clock for the TBU. - Fix error handling if level 1 CD table allocation fails. - Permit more than the architectural maximum number of SMRs for funky Qualcomm mis-implementations of SMMUv2. - Mediatek driver: - MT8189 iommu support - Move ARM IO-pgtable selftests to kunit - Device leak fixes for a couple of drivers - Random smaller fixes and improvements * tag 'iommu-updates-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: (81 commits) iommupt/vtd: Support mgaw's less than a 4 level walk for first stage iommupt/vtd: Allow VT-d to have a larger table top than the vasz requires powerpc/pseries/svm: Make mem_encrypt.h self contained genpt: Make GENERIC_PT invisible iommupt: Avoid a compiler bug with sw_bit iommu/arm-smmu-qcom: Enable use of all SMR groups when running bare-metal iommupt: Fix unlikely flows in increase_top() iommu/amd: Propagate the error code returned by __modify_irte_ga() in modify_irte_ga() MAINTAINERS: Update my email address iommu/arm-smmu-v3: Fix error check in arm_smmu_alloc_cd_tables dt-bindings: iommu: qcom_iommu: Allow 'tbu' clock iommu/vt-d: Restore previous domain::aperture_end calculation iommu/vt-d: Fix unused invalidation hint in qi_desc_iotlb iommu/vt-d: Set INTEL_IOMMU_FLOPPY_WA depend on BLK_DEV_FD iommu/tegra: fix device leak on probe_device() iommu/sun50i: fix device leak on of_xlate() iommu/omap: simplify probe_device() error handling iommu/omap: fix device leaks on probe_device() iommu/mediatek-v1: add missing larb count sanity check iommu/mediatek-v1: fix device leaks on probe() ...
2 parents 5797d10 + 0d081b1 commit ce5cfb0

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.clang-format

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@@ -415,6 +415,7 @@ ForEachMacros:
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- 'for_each_prop_dlc_cpus'
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- 'for_each_prop_dlc_platforms'
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- 'for_each_property_of_node'
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- 'for_each_pt_level_entry'
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- 'for_each_rdt_resource'
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- 'for_each_reg'
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- 'for_each_reg_filtered'

.mailmap

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@@ -345,7 +345,8 @@ Jayachandran C <c.jayachandran@gmail.com> <jayachandranc@netlogicmicro.com>
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Jayachandran C <c.jayachandran@gmail.com> <jchandra@broadcom.com>
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Jayachandran C <c.jayachandran@gmail.com> <jchandra@digeo.com>
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Jayachandran C <c.jayachandran@gmail.com> <jnair@caviumnetworks.com>
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<jean-philippe@linaro.org> <jean-philippe.brucker@arm.com>
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Jean-Philippe Brucker <jpb@kernel.org> <jean-philippe.brucker@arm.com>
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Jean-Philippe Brucker <jpb@kernel.org> <jean-philippe@linaro.org>
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Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org> <jeanmichel.hautbois@ideasonboard.com>
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Jean Tourrilhes <jt@hpl.hp.com>
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Jeevan Shriram <quic_jshriram@quicinc.com> <jshriram@codeaurora.org>

Documentation/devicetree/bindings/iommu/arm,smmu.yaml

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- description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
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items:
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- enum:
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- qcom,glymur-smmu-500
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- qcom,kaanapali-smmu-500
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- qcom,milos-smmu-500
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- qcom,qcm2290-smmu-500
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- qcom,qcs615-smmu-500

Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml

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- mediatek,mt8188-iommu-vdo # generation two
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- mediatek,mt8188-iommu-vpp # generation two
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- mediatek,mt8188-iommu-infra # generation two
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- mediatek,mt8189-iommu-apu # generation two
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- mediatek,mt8189-iommu-infra # generation two
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- mediatek,mt8189-iommu-mm # generation two
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- mediatek,mt8192-m4u # generation two
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- mediatek,mt8195-iommu-vdo # generation two
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- mediatek,mt8195-iommu-vpp # generation two
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This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as
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defined in
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dt-binding/memory/mediatek,mt8188-memory-port.h for mt8188,
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dt-binding/memory/mediatek,mt8189-memory-port.h for mt8189,
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dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623,
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dt-binding/memory/mt2712-larb-port.h for mt2712,
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dt-binding/memory/mt6779-larb-port.h for mt6779,
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- mediatek,mt8186-iommu-mm
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- mediatek,mt8188-iommu-vdo
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- mediatek,mt8188-iommu-vpp
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- mediatek,mt8189-iommu-mm
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- mediatek,mt8192-m4u
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- mediatek,mt8195-iommu-vdo
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- mediatek,mt8195-iommu-vpp
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- mediatek,mt8188-iommu-vdo
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- mediatek,mt8188-iommu-vpp
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- mediatek,mt8189-iommu-mm
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- mediatek,mt8195-iommu-vpp
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- mediatek,mt8188-iommu-infra
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- mediatek,mt8189-iommu-apu
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- mediatek,mt8189-iommu-infra
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- mediatek,mt8195-iommu-infra
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then:

Documentation/devicetree/bindings/iommu/qcom,iommu.yaml

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- const: qcom,msm-iommu-v2
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clocks:
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minItems: 2
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- description: Clock required for IOMMU register group access
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- description: Clock required for underlying bus access
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- description: Clock required for Translation Buffer Unit access
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clock-names:
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minItems: 2
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- const: iface
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- const: bus
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- const: tbu
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power-domains:
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maxItems: 1
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.. SPDX-License-Identifier: GPL-2.0
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========================
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Generic Radix Page Table
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========================
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.. kernel-doc:: include/linux/generic_pt/common.h
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:doc: Generic Radix Page Table
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.. kernel-doc:: drivers/iommu/generic_pt/pt_defs.h
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:doc: Generic Page Table Language
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Usage
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=====
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Generic PT is structured as a multi-compilation system. Since each format
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provides an API using a common set of names there can be only one format active
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within a compilation unit. This design avoids function pointers around the low
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level API.
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Instead the function pointers can end up at the higher level API (i.e.
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map/unmap, etc.) and the per-format code can be directly inlined into the
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per-format compilation unit. For something like IOMMU each format will be
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compiled into a per-format IOMMU operations kernel module.
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For this to work the .c file for each compilation unit will include both the
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format headers and the generic code for the implementation. For instance in an
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implementation compilation unit the headers would normally be included as
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follows:
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generic_pt/fmt/iommu_amdv1.c::
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#include <linux/generic_pt/common.h>
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#include "defs_amdv1.h"
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#include "../pt_defs.h"
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#include "amdv1.h"
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#include "../pt_common.h"
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#include "../pt_iter.h"
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#include "../iommu_pt.h" /* The IOMMU implementation */
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iommu_pt.h includes definitions that will generate the operations functions for
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map/unmap/etc. using the definitions provided by AMDv1. The resulting module
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will have exported symbols named like pt_iommu_amdv1_init().
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Refer to drivers/iommu/generic_pt/fmt/iommu_template.h for an example of how the
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IOMMU implementation uses multi-compilation to generate per-format ops structs
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pointers.
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The format code is written so that the common names arise from #defines to
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distinct format specific names. This is intended to aid debuggability by
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avoiding symbol clashes across all the different formats.
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Exported symbols and other global names are mangled using a per-format string
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via the NS() helper macro.
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The format uses struct pt_common as the top-level struct for the table,
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and each format will have its own struct pt_xxx which embeds it to store
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format-specific information.
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The implementation will further wrap struct pt_common in its own top-level
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struct, such as struct pt_iommu_amdv1.
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Format functions at the struct pt_common level
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----------------------------------------------
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.. kernel-doc:: include/linux/generic_pt/common.h
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:identifiers:
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.. kernel-doc:: drivers/iommu/generic_pt/pt_common.h
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Iteration Helpers
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-----------------
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.. kernel-doc:: drivers/iommu/generic_pt/pt_iter.h
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Writing a Format
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----------------
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It is best to start from a simple format that is similar to the target. x86_64
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is usually a good reference for something simple, and AMDv1 is something fairly
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complete.
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The required inline functions need to be implemented in the format header.
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These should all follow the standard pattern of::
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static inline pt_oaddr_t amdv1pt_entry_oa(const struct pt_state *pts)
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{
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[..]
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}
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#define pt_entry_oa amdv1pt_entry_oa
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where a uniquely named per-format inline function provides the implementation
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and a define maps it to the generic name. This is intended to make debug symbols
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work better. inline functions should always be used as the prototypes in
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pt_common.h will cause the compiler to validate the function signature to
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prevent errors.
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Review pt_fmt_defaults.h to understand some of the optional inlines.
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Once the format compiles then it should be run through the generic page table
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kunit test in kunit_generic_pt.h using kunit. For example::
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$ tools/testing/kunit/kunit.py run --build_dir build_kunit_x86_64 --arch x86_64 --kunitconfig ./drivers/iommu/generic_pt/.kunitconfig amdv1_fmt_test.*
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[...]
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[11:15:08] Testing complete. Ran 9 tests: passed: 9
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[11:15:09] Elapsed time: 3.137s total, 0.001s configuring, 2.368s building, 0.311s running
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The generic tests are intended to prove out the format functions and give
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clearer failures to speed up finding the problems. Once those pass then the
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entire kunit suite should be run.
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IOMMU Invalidation Features
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---------------------------
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Invalidation is how the page table algorithms synchronize with a HW cache of the
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page table memory, typically called the TLB (or IOTLB for IOMMU cases).
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The TLB can store present PTEs, non-present PTEs and table pointers, depending
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on its design. Every HW has its own approach on how to describe what has changed
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to have changed items removed from the TLB.
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PT_FEAT_FLUSH_RANGE
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~~~~~~~~~~~~~~~~~~~
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PT_FEAT_FLUSH_RANGE is the easiest scheme to understand. It tries to generate a
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single range invalidation for each operation, over-invalidating if there are
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gaps of VA that don't need invalidation. This trades off impacted VA for number
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of invalidation operations. It does not keep track of what is being invalidated;
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however, if pages have to be freed then page table pointers have to be cleaned
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from the walk cache. The range can start/end at any page boundary.
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PT_FEAT_FLUSH_RANGE_NO_GAPS
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~~~~~~~~~~~~~~~~~~~~~~~~~~~
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PT_FEAT_FLUSH_RANGE_NO_GAPS is similar to PT_FEAT_FLUSH_RANGE; however, it tries
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to minimize the amount of impacted VA by issuing extra flush operations. This is
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useful if the cost of processing VA is very high, for instance because a
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hypervisor is processing the page table with a shadowing algorithm.

Documentation/driver-api/index.rst

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frame-buffer
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aperture
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generic_pt
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gpio/index
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hsi
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hte/index

MAINTAINERS

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ACPI VIOT DRIVER
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M: Jean-Philippe Brucker <jean-philippe@linaro.org>
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M: Jean-Philippe Brucker <jpb@kernel.org>
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L: linux-acpi@vger.kernel.org
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ARM SMMU SVA SUPPORT
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ARM SUB-ARCHITECTURES
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VIRTIO IOMMU DRIVER
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L: virtualization@lists.linux.dev
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arch/powerpc/include/asm/mem_encrypt.h

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struct device;
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arch/powerpc/kernel/iommu.c

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struct device *dev, struct iommu_domain *old)
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{
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struct iommu_group *grp = iommu_group_get(dev);
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struct iommu_table_group *table_group;

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