Skip to content

Commit ce8ab92

Browse files
wensbroonie
wens
authored and
broonie
committed
regulator: mt6358: Add supply names for MT6366 regulators
The DT bindings for MT6366 regulator defines the supply names for the PMIC. Add support for them by adding .supply_name field settings for each regulator. The buck regulators each have their own supply whose name can be derived from the regulator name. The LDOs have shared supplies. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230928085537.3246669-12-wenst@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
1 parent b7768e6 commit ce8ab92

1 file changed

Lines changed: 37 additions & 40 deletions

File tree

‎drivers/regulator/mt6358-regulator.c‎

Lines changed: 37 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -140,6 +140,7 @@ struct mt6358_regulator_info {
140140
[MT6366_ID_##vreg] = { \
141141
.desc = { \
142142
.name = #vreg, \
143+
.supply_name = "vsys-" match, \
143144
.of_match = of_match_ptr(match), \
144145
.ops = &mt6358_volt_range_ops, \
145146
.type = REGULATOR_VOLTAGE, \
@@ -162,10 +163,11 @@ struct mt6358_regulator_info {
162163
.modeset_mask = BIT(_modeset_shift), \
163164
}
164165

165-
#define MT6366_LDO(match, vreg, volt_ranges, enreg, enbit, vosel, vosel_mask) \
166+
#define MT6366_LDO(match, vreg, volt_ranges, supply, enreg, enbit, vosel, vosel_mask) \
166167
[MT6366_ID_##vreg] = { \
167168
.desc = { \
168169
.name = #vreg, \
170+
.supply_name = supply, \
169171
.of_match = of_match_ptr(match), \
170172
.ops = &mt6358_volt_table_ops, \
171173
.type = REGULATOR_VOLTAGE, \
@@ -186,12 +188,12 @@ struct mt6358_regulator_info {
186188
.qi = BIT(15), \
187189
}
188190

189-
#define MT6366_LDO1(match, vreg, min, max, step, \
190-
_da_vsel_reg, _da_vsel_mask, \
191-
vosel, vosel_mask) \
191+
#define MT6366_LDO1(match, vreg, supply, min, max, step, \
192+
_da_vsel_reg, _da_vsel_mask, vosel, vosel_mask) \
192193
[MT6366_ID_##vreg] = { \
193194
.desc = { \
194195
.name = #vreg, \
196+
.supply_name = supply, \
195197
.of_match = of_match_ptr(match), \
196198
.ops = &mt6358_volt_range_ops, \
197199
.type = REGULATOR_VOLTAGE, \
@@ -211,11 +213,11 @@ struct mt6358_regulator_info {
211213
.qi = BIT(0), \
212214
}
213215

214-
#define MT6366_REG_FIXED(match, vreg, \
215-
enreg, enbit, volt) \
216+
#define MT6366_REG_FIXED(match, vreg, supply, enreg, enbit, volt) \
216217
[MT6366_ID_##vreg] = { \
217218
.desc = { \
218219
.name = #vreg, \
220+
.supply_name = supply, \
219221
.of_match = of_match_ptr(match), \
220222
.ops = &mt6358_volt_fixed_ops, \
221223
.type = REGULATOR_VOLTAGE, \
@@ -578,57 +580,52 @@ static const struct mt6358_regulator_info mt6366_regulators[] = {
578580
0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f, MT6358_VMODEM_ANA_CON0, 8),
579581
MT6366_BUCK("vs1", VS1, 1000000, 2587500, 12500,
580582
0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, MT6358_VS1_ANA_CON0, 8),
581-
MT6366_REG_FIXED("vrf12", VRF12,
582-
MT6358_LDO_VRF12_CON0, 0, 1200000),
583-
MT6366_REG_FIXED("vio18", VIO18,
584-
MT6358_LDO_VIO18_CON0, 0, 1800000),
585-
MT6366_REG_FIXED("vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
586-
MT6366_REG_FIXED("vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
587-
MT6366_REG_FIXED("vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
588-
MT6366_REG_FIXED("vaux18", VAUX18,
589-
MT6358_LDO_VAUX18_CON0, 0, 1800000),
590-
MT6366_REG_FIXED("vbif28", VBIF28,
591-
MT6358_LDO_VBIF28_CON0, 0, 2800000),
592-
MT6366_REG_FIXED("vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
593-
MT6366_REG_FIXED("va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
594-
MT6366_REG_FIXED("vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
595-
MT6366_REG_FIXED("vaud28", VAUD28,
596-
MT6358_LDO_VAUD28_CON0, 0, 2800000),
597-
MT6366_LDO("vdram2", VDRAM2, vdram2,
583+
MT6366_REG_FIXED("vrf12", VRF12, "vs2-ldo2", MT6358_LDO_VRF12_CON0, 0, 1200000),
584+
MT6366_REG_FIXED("vio18", VIO18, "vs1-ldo1", MT6358_LDO_VIO18_CON0, 0, 1800000),
585+
MT6366_REG_FIXED("vfe28", VFE28, "vsys-ldo1", MT6358_LDO_VFE28_CON0, 0, 2800000),
586+
MT6366_REG_FIXED("vcn28", VCN28, "vsys-ldo1", MT6358_LDO_VCN28_CON0, 0, 2800000),
587+
MT6366_REG_FIXED("vxo22", VXO22, "vsys-ldo1", MT6358_LDO_VXO22_CON0, 0, 2200000),
588+
MT6366_REG_FIXED("vaux18", VAUX18, "vsys-ldo1", MT6358_LDO_VAUX18_CON0, 0, 1800000),
589+
MT6366_REG_FIXED("vbif28", VBIF28, "vsys-ldo1", MT6358_LDO_VBIF28_CON0, 0, 2800000),
590+
MT6366_REG_FIXED("vio28", VIO28, "vsys-ldo2", MT6358_LDO_VIO28_CON0, 0, 2800000),
591+
MT6366_REG_FIXED("va12", VA12, "vs2-ldo2", MT6358_LDO_VA12_CON0, 0, 1200000),
592+
MT6366_REG_FIXED("vrf18", VRF18, "vs1-ldo1", MT6358_LDO_VRF18_CON0, 0, 1800000),
593+
MT6366_REG_FIXED("vaud28", VAUD28, "vsys-ldo1", MT6358_LDO_VAUD28_CON0, 0, 2800000),
594+
MT6366_LDO("vdram2", VDRAM2, vdram2, "vs2-ldo1",
598595
MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0x10),
599-
MT6366_LDO("vsim1", VSIM1, vsim,
596+
MT6366_LDO("vsim1", VSIM1, vsim, "vsys-ldo1",
600597
MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00),
601-
MT6366_LDO("vibr", VIBR, vibr,
598+
MT6366_LDO("vibr", VIBR, vibr, "vsys-ldo3",
602599
MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00),
603-
MT6366_LDO("vusb", VUSB, vusb,
600+
MT6366_LDO("vusb", VUSB, vusb, "vsys-ldo1",
604601
MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700),
605-
MT6366_LDO("vefuse", VEFUSE, vefuse,
602+
MT6366_LDO("vefuse", VEFUSE, vefuse, "vs1-ldo1",
606603
MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00),
607-
MT6366_LDO("vmch", VMCH, vmch_vemc,
604+
MT6366_LDO("vmch", VMCH, vmch_vemc, "vsys-ldo2",
608605
MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700),
609-
MT6366_LDO("vemc", VEMC, vmch_vemc,
606+
MT6366_LDO("vemc", VEMC, vmch_vemc, "vsys-ldo3",
610607
MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700),
611-
MT6366_LDO("vcn33", VCN33, vcn33,
608+
MT6366_LDO("vcn33", VCN33, vcn33, "vsys-ldo3",
612609
MT6358_LDO_VCN33_CON0_0, 0, MT6358_VCN33_ANA_CON0, 0x300),
613-
MT6366_LDO("vmc", VMC, vmc,
610+
MT6366_LDO("vmc", VMC, vmc, "vsys-ldo2",
614611
MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00),
615-
MT6366_LDO("vsim2", VSIM2, vsim,
612+
MT6366_LDO("vsim2", VSIM2, vsim, "vsys-ldo2",
616613
MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00),
617-
MT6366_LDO("vcn18", VCN18, mt6366_vcn18_vm18,
614+
MT6366_LDO("vcn18", VCN18, mt6366_vcn18_vm18, "vs1-ldo1",
618615
MT6358_LDO_VCN18_CON0, 0, MT6358_VCN18_ANA_CON0, 0xf00),
619-
MT6366_LDO("vm18", VM18, mt6366_vcn18_vm18,
616+
MT6366_LDO("vm18", VM18, mt6366_vcn18_vm18, "vs1-ldo1",
620617
MT6358_LDO_VM18_CON0, 0, MT6358_VM18_ANA_CON0, 0xf00),
621-
MT6366_LDO("vmddr", VMDDR, mt6366_vmddr,
618+
MT6366_LDO("vmddr", VMDDR, mt6366_vmddr, "vs2-ldo1",
622619
MT6358_LDO_VMDDR_CON0, 0, MT6358_VMDDR_ANA_CON0, 0xf00),
623-
MT6366_LDO1("vsram-proc11", VSRAM_PROC11, 500000, 1293750, 6250,
620+
MT6366_LDO1("vsram-proc11", VSRAM_PROC11, "vs2-ldo3", 500000, 1293750, 6250,
624621
MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON0, 0x7f),
625-
MT6366_LDO1("vsram-others", VSRAM_OTHERS, 500000, 1293750, 6250,
622+
MT6366_LDO1("vsram-others", VSRAM_OTHERS, "vs2-ldo3", 500000, 1293750, 6250,
626623
MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON2, 0x7f),
627-
MT6366_LDO1("vsram-gpu", VSRAM_GPU, 500000, 1293750, 6250,
624+
MT6366_LDO1("vsram-gpu", VSRAM_GPU, "vs2-ldo3", 500000, 1293750, 6250,
628625
MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON3, 0x7f),
629-
MT6366_LDO1("vsram-proc12", VSRAM_PROC12, 500000, 1293750, 6250,
626+
MT6366_LDO1("vsram-proc12", VSRAM_PROC12, "vs2-ldo3", 500000, 1293750, 6250,
630627
MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON1, 0x7f),
631-
MT6366_LDO1("vsram-core", VSRAM_CORE, 500000, 1293750, 6250,
628+
MT6366_LDO1("vsram-core", VSRAM_CORE, "vs2-ldo3", 500000, 1293750, 6250,
632629
MT6358_LDO_VSRAM_CORE_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON5, 0x7f),
633630
};
634631

0 commit comments

Comments
 (0)