drm/i915: Enable per-lane DP drive settings for bxt/glk

vsyrjala · vsyrjala · commit d08184aa9065 · 2024-04-19T19:47:22.000+03:00
Now the bxt/glk PHY code is ready for per-lane drive settings so enable it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240412175818.29217-9-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -334,7 +334,7 @@ static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 
 	return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) ||
-		DISPLAY_VER(i915) >= 11;
+		DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915);
 }
 
 /* 128b/132b */

Original file line number	Diff line number	Diff line change
`@@ -334,7 +334,7 @@ static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,`
`334`	`334`	`struct drm_i915_private *i915 = dp_to_i915(intel_dp);`
`335`	`335`
`336`	`336`	`return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) \|\|`
`337`		`- DISPLAY_VER(i915) >= 11;`
	`337`	`+ DISPLAY_VER(i915) >= 10 \|\| IS_BROXTON(i915);`
`338`	`338`	`}`
`339`	`339`
`340`	`340`	`/* 128b/132b */`