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jernejskwens
jernejsk
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wens
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drm/sun4i: mixer: split out layer config
Later special plane only driver for DE33 will provide separate configuration. This change will also help layer driver migrate away from mixer structure. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-28-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
1 parent 5a96ae8 commit d1fe263

6 files changed

Lines changed: 123 additions & 76 deletions

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‎drivers/gpu/drm/sun4i/sun8i_csc.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -240,7 +240,7 @@ void sun8i_csc_config(struct sun8i_layer *layer,
240240
return;
241241
}
242242

243-
base = ccsc_base[layer->mixer->cfg->ccsc][layer->channel];
243+
base = ccsc_base[layer->mixer->cfg->lay_cfg.ccsc][layer->channel];
244244

245245
sun8i_csc_setup(layer->regs, base,
246246
mode, state->color_encoding,

‎drivers/gpu/drm/sun4i/sun8i_mixer.c‎

Lines changed: 94 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -704,137 +704,173 @@ static void sun8i_mixer_remove(struct platform_device *pdev)
704704
}
705705

706706
static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = {
707-
.ccsc = CCSC_MIXER0_LAYOUT,
707+
.lay_cfg = {
708+
.ccsc = CCSC_MIXER0_LAYOUT,
709+
.de_type = SUN8I_MIXER_DE2,
710+
.vi_scaler_num = 1,
711+
.scaler_mask = 0xf,
712+
.scanline_yuv = 2048,
713+
.de2_fcc_alpha = 1,
714+
},
708715
.de_type = SUN8I_MIXER_DE2,
709-
.vi_scaler_num = 1,
710-
.scaler_mask = 0xf,
711-
.scanline_yuv = 2048,
712-
.de2_fcc_alpha = 1,
713716
.ui_num = 3,
714717
.vi_num = 1,
715718
};
716719

717720
static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = {
718-
.ccsc = CCSC_MIXER1_LAYOUT,
721+
.lay_cfg = {
722+
.ccsc = CCSC_MIXER1_LAYOUT,
723+
.de_type = SUN8I_MIXER_DE2,
724+
.vi_scaler_num = 1,
725+
.scaler_mask = 0x3,
726+
.scanline_yuv = 2048,
727+
.de2_fcc_alpha = 1,
728+
},
719729
.de_type = SUN8I_MIXER_DE2,
720-
.vi_scaler_num = 1,
721-
.scaler_mask = 0x3,
722-
.scanline_yuv = 2048,
723-
.de2_fcc_alpha = 1,
724730
.ui_num = 1,
725731
.vi_num = 1,
726732
};
727733

728734
static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
729-
.ccsc = CCSC_MIXER0_LAYOUT,
735+
.lay_cfg = {
736+
.ccsc = CCSC_MIXER0_LAYOUT,
737+
.de_type = SUN8I_MIXER_DE2,
738+
.vi_scaler_num = 1,
739+
.scaler_mask = 0xf,
740+
.scanline_yuv = 2048,
741+
.de2_fcc_alpha = 1,
742+
},
730743
.de_type = SUN8I_MIXER_DE2,
731744
.mod_rate = 432000000,
732-
.vi_scaler_num = 1,
733-
.scaler_mask = 0xf,
734-
.scanline_yuv = 2048,
735-
.de2_fcc_alpha = 1,
736745
.ui_num = 3,
737746
.vi_num = 1,
738747
};
739748

740749
static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
741-
.ccsc = CCSC_MIXER0_LAYOUT,
750+
.lay_cfg = {
751+
.ccsc = CCSC_MIXER0_LAYOUT,
752+
.de_type = SUN8I_MIXER_DE2,
753+
.vi_scaler_num = 1,
754+
.scaler_mask = 0xf,
755+
.scanline_yuv = 2048,
756+
.de2_fcc_alpha = 1,
757+
},
742758
.de_type = SUN8I_MIXER_DE2,
743759
.mod_rate = 297000000,
744-
.vi_scaler_num = 1,
745-
.scaler_mask = 0xf,
746-
.scanline_yuv = 2048,
747-
.de2_fcc_alpha = 1,
748760
.ui_num = 3,
749761
.vi_num = 1,
750762
};
751763

752764
static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
753-
.ccsc = CCSC_MIXER1_LAYOUT,
765+
.lay_cfg = {
766+
.ccsc = CCSC_MIXER1_LAYOUT,
767+
.de_type = SUN8I_MIXER_DE2,
768+
.vi_scaler_num = 1,
769+
.scaler_mask = 0x3,
770+
.scanline_yuv = 2048,
771+
.de2_fcc_alpha = 1,
772+
},
754773
.de_type = SUN8I_MIXER_DE2,
755774
.mod_rate = 297000000,
756-
.vi_scaler_num = 1,
757-
.scaler_mask = 0x3,
758-
.scanline_yuv = 2048,
759-
.de2_fcc_alpha = 1,
760775
.ui_num = 1,
761776
.vi_num = 1,
762777
};
763778

764779
static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
765-
.de_type = SUN8I_MIXER_DE2,
766-
.vi_num = 2,
767-
.ui_num = 1,
768-
.vi_scaler_num = 2,
769-
.scaler_mask = 0x3,
770-
.scanline_yuv = 2048,
771-
.ccsc = CCSC_MIXER0_LAYOUT,
772-
.mod_rate = 150000000,
780+
.lay_cfg = {
781+
.ccsc = CCSC_MIXER0_LAYOUT,
782+
.de_type = SUN8I_MIXER_DE2,
783+
.vi_scaler_num = 2,
784+
.scaler_mask = 0x3,
785+
.scanline_yuv = 2048,
786+
},
787+
.de_type = SUN8I_MIXER_DE2,
788+
.mod_rate = 150000000,
789+
.vi_num = 2,
790+
.ui_num = 1,
773791
};
774792

775793
static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = {
776-
.ccsc = CCSC_D1_MIXER0_LAYOUT,
794+
.lay_cfg = {
795+
.ccsc = CCSC_D1_MIXER0_LAYOUT,
796+
.de_type = SUN8I_MIXER_DE2,
797+
.vi_scaler_num = 1,
798+
.scaler_mask = 0x3,
799+
.scanline_yuv = 2048,
800+
.de2_fcc_alpha = 1,
801+
},
777802
.de_type = SUN8I_MIXER_DE2,
778803
.mod_rate = 297000000,
779-
.vi_scaler_num = 1,
780-
.scaler_mask = 0x3,
781-
.scanline_yuv = 2048,
782-
.de2_fcc_alpha = 1,
783804
.ui_num = 1,
784805
.vi_num = 1,
785806
};
786807

787808
static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = {
788-
.ccsc = CCSC_MIXER1_LAYOUT,
809+
.lay_cfg = {
810+
.ccsc = CCSC_MIXER1_LAYOUT,
811+
.de_type = SUN8I_MIXER_DE2,
812+
.vi_scaler_num = 1,
813+
.scaler_mask = 0x1,
814+
.scanline_yuv = 1024,
815+
.de2_fcc_alpha = 1,
816+
},
789817
.de_type = SUN8I_MIXER_DE2,
790818
.mod_rate = 297000000,
791-
.vi_scaler_num = 1,
792-
.scaler_mask = 0x1,
793-
.scanline_yuv = 1024,
794-
.de2_fcc_alpha = 1,
795819
.ui_num = 0,
796820
.vi_num = 1,
797821
};
798822

799823
static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = {
800-
.ccsc = CCSC_MIXER0_LAYOUT,
824+
.lay_cfg = {
825+
.ccsc = CCSC_MIXER0_LAYOUT,
826+
.de_type = SUN8I_MIXER_DE2,
827+
.vi_scaler_num = 1,
828+
.scaler_mask = 0xf,
829+
.scanline_yuv = 4096,
830+
.de2_fcc_alpha = 1,
831+
},
801832
.de_type = SUN8I_MIXER_DE2,
802833
.mod_rate = 297000000,
803-
.vi_scaler_num = 1,
804-
.scaler_mask = 0xf,
805-
.scanline_yuv = 4096,
806-
.de2_fcc_alpha = 1,
807834
.ui_num = 3,
808835
.vi_num = 1,
809836
};
810837

811838
static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
812-
.ccsc = CCSC_MIXER1_LAYOUT,
839+
.lay_cfg = {
840+
.ccsc = CCSC_MIXER1_LAYOUT,
841+
.de_type = SUN8I_MIXER_DE2,
842+
.vi_scaler_num = 1,
843+
.scaler_mask = 0x3,
844+
.scanline_yuv = 2048,
845+
.de2_fcc_alpha = 1,
846+
},
813847
.de_type = SUN8I_MIXER_DE2,
814848
.mod_rate = 297000000,
815-
.vi_scaler_num = 1,
816-
.scaler_mask = 0x3,
817-
.scanline_yuv = 2048,
818-
.de2_fcc_alpha = 1,
819849
.ui_num = 1,
820850
.vi_num = 1,
821851
};
822852

823853
static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = {
854+
.lay_cfg = {
855+
.de_type = SUN8I_MIXER_DE3,
856+
.vi_scaler_num = 1,
857+
.scaler_mask = 0xf,
858+
.scanline_yuv = 4096,
859+
},
824860
.de_type = SUN8I_MIXER_DE3,
825861
.mod_rate = 600000000,
826-
.vi_scaler_num = 1,
827-
.scaler_mask = 0xf,
828-
.scanline_yuv = 4096,
829862
.ui_num = 3,
830863
.vi_num = 1,
831864
};
832865

833866
static const struct sun8i_mixer_cfg sun50i_h616_mixer0_cfg = {
867+
.lay_cfg = {
868+
.de_type = SUN8I_MIXER_DE33,
869+
.scaler_mask = 0xf,
870+
.scanline_yuv = 4096,
871+
},
834872
.de_type = SUN8I_MIXER_DE33,
835873
.mod_rate = 600000000,
836-
.scaler_mask = 0xf,
837-
.scanline_yuv = 4096,
838874
.ui_num = 3,
839875
.vi_num = 1,
840876
.map = {0, 6, 7, 8},

‎drivers/gpu/drm/sun4i/sun8i_mixer.h‎

Lines changed: 22 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -164,34 +164,45 @@ enum sun8i_mixer_type {
164164
};
165165

166166
/**
167-
* struct sun8i_mixer_cfg - mixer HW configuration
168-
* @vi_num: number of VI channels
169-
* @ui_num: number of UI channels
167+
* struct sun8i_layer_cfg - layer configuration
170168
* @vi_scaler_num: Number of VI scalers. Used on DE2 and DE3.
171169
* @scaler_mask: bitmask which tells which channel supports scaling
172170
* First, scaler supports for VI channels is defined and after that, scaler
173171
* support for UI channels. For example, if mixer has 2 VI channels without
174172
* scaler and 2 UI channels with scaler, bitmask would be 0xC.
175173
* @ccsc: select set of CCSC base addresses from the enumeration above.
176-
* @mod_rate: module clock rate that needs to be set in order to have
177-
* a functional block.
178174
* @de_type: sun8i_mixer_type enum representing the display engine generation.
179175
* @scaline_yuv: size of a scanline for VI scaler for YUV formats.
180176
* @de2_fcc_alpha: use FCC for missing DE2 VI alpha capability
181177
* Most DE2 cores has FCC. If number of VI planes is one, enable this.
182-
* @map: channel map for DE variants processing YUV separately (DE33)
183178
*/
184-
struct sun8i_mixer_cfg {
185-
int vi_num;
186-
int ui_num;
179+
struct sun8i_layer_cfg {
187180
unsigned int vi_scaler_num;
188181
int scaler_mask;
189182
int ccsc;
190-
unsigned long mod_rate;
191183
unsigned int de_type;
192184
unsigned int scanline_yuv;
193185
unsigned int de2_fcc_alpha : 1;
194-
unsigned int map[6];
186+
};
187+
188+
/**
189+
* struct sun8i_mixer_cfg - mixer HW configuration
190+
* @lay_cfg: layer configuration
191+
* @vi_num: number of VI channels
192+
* @ui_num: number of UI channels
193+
* @de_type: sun8i_mixer_type enum representing the display engine generation.
194+
* @mod_rate: module clock rate that needs to be set in order to have
195+
* a functional block.
196+
* @map: channel map for DE variants processing YUV separately (DE33)
197+
*/
198+
199+
struct sun8i_mixer_cfg {
200+
struct sun8i_layer_cfg lay_cfg;
201+
int vi_num;
202+
int ui_num;
203+
unsigned int de_type;
204+
unsigned long mod_rate;
205+
unsigned int map[6];
195206
};
196207

197208
struct sun8i_mixer {

‎drivers/gpu/drm/sun4i/sun8i_ui_layer.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -190,7 +190,7 @@ static int sun8i_ui_layer_atomic_check(struct drm_plane *plane,
190190
min_scale = DRM_PLANE_NO_SCALING;
191191
max_scale = DRM_PLANE_NO_SCALING;
192192

193-
if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) {
193+
if (layer->mixer->cfg->lay_cfg.scaler_mask & BIT(layer->channel)) {
194194
min_scale = SUN8I_UI_SCALER_SCALE_MIN;
195195
max_scale = SUN8I_UI_SCALER_SCALE_MAX;
196196
}

‎drivers/gpu/drm/sun4i/sun8i_ui_scaler.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ static const u32 lan2coefftab16[240] = {
9191

9292
static u32 sun8i_ui_scaler_base(struct sun8i_mixer *mixer, int channel)
9393
{
94-
int offset = mixer->cfg->vi_scaler_num;
94+
int offset = mixer->cfg->lay_cfg.vi_scaler_num;
9595

9696
if (mixer->cfg->de_type == SUN8I_MIXER_DE3)
9797
return DE3_VI_SCALER_UNIT_BASE +

‎drivers/gpu/drm/sun4i/sun8i_vi_layer.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ static void sun8i_vi_layer_update_attributes(struct sun8i_layer *layer,
5454
regmap_write(layer->regs,
5555
SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay), val);
5656

57-
if (mixer->cfg->de2_fcc_alpha) {
57+
if (mixer->cfg->lay_cfg.de2_fcc_alpha) {
5858
regmap_write(layer->regs,
5959
SUN8I_MIXER_FCC_GLOBAL_ALPHA_REG,
6060
SUN8I_MIXER_FCC_GLOBAL_ALPHA(state->alpha >> 8));
@@ -153,7 +153,7 @@ static void sun8i_vi_layer_update_coord(struct sun8i_layer *layer,
153153
}
154154

155155
/* it seems that every RGB scaler has buffer for 2048 pixels */
156-
scanline = subsampled ? mixer->cfg->scanline_yuv : 2048;
156+
scanline = subsampled ? mixer->cfg->lay_cfg.scanline_yuv : 2048;
157157

158158
if (src_w > scanline) {
159159
DRM_DEBUG_DRIVER("Using horizontal coarse scaling\n");
@@ -278,7 +278,7 @@ static int sun8i_vi_layer_atomic_check(struct drm_plane *plane,
278278
min_scale = DRM_PLANE_NO_SCALING;
279279
max_scale = DRM_PLANE_NO_SCALING;
280280

281-
if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) {
281+
if (layer->mixer->cfg->lay_cfg.scaler_mask & BIT(layer->channel)) {
282282
min_scale = SUN8I_VI_SCALER_SCALE_MIN;
283283
max_scale = SUN8I_VI_SCALER_SCALE_MAX;
284284
}
@@ -452,7 +452,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
452452
return ERR_PTR(ret);
453453
}
454454

455-
if (mixer->cfg->de2_fcc_alpha || mixer->cfg->de_type >= SUN8I_MIXER_DE3) {
455+
if (mixer->cfg->lay_cfg.de2_fcc_alpha || mixer->cfg->de_type >= SUN8I_MIXER_DE3) {
456456
ret = drm_plane_create_alpha_property(&layer->plane);
457457
if (ret) {
458458
dev_err(drm->dev, "Couldn't add alpha property\n");

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