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clk: mediatek: Add MT8196 mcu clock support
Add support for the MT8196 mcu clock controller, which provides PLL control for MCU. Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Laura Nao <laura.nao@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Lines changed: 175 additions & 0 deletions

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‎drivers/clk/mediatek/Kconfig‎

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@@ -1017,6 +1017,13 @@ config COMMON_CLK_MT8196_IMP_IIC_WRAP
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help
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This driver supports MediaTek MT8196 i2c clocks.
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config COMMON_CLK_MT8196_MCUSYS
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tristate "Clock driver for MediaTek MT8196 mcusys"
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depends on COMMON_CLK_MT8196
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default COMMON_CLK_MT8196
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help
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This driver supports MediaTek MT8196 mcusys clocks.
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config COMMON_CLK_MT8196_PEXTPSYS
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tristate "Clock driver for MediaTek MT8196 pextpsys"
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depends on COMMON_CLK_MT8196

‎drivers/clk/mediatek/Makefile‎

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@@ -154,6 +154,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-topckgen.o
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clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \
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clk-mt8196-peri_ao.o
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obj-$(CONFIG_COMMON_CLK_MT8196_IMP_IIC_WRAP) += clk-mt8196-imp_iic_wrap.o
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obj-$(CONFIG_COMMON_CLK_MT8196_MCUSYS) += clk-mt8196-mcu.o
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obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o
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obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o
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obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o

‎drivers/clk/mediatek/clk-mt8196-mcu.c‎

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2025 MediaTek Inc.
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* Guangjie Song <guangjie.song@mediatek.com>
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* Copyright (c) 2025 Collabora Ltd.
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* Laura Nao <laura.nao@collabora.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8196-clock.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-pll.h"
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#define ARMPLL_LL_CON0 0x008
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#define ARMPLL_LL_CON1 0x00c
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#define ARMPLL_LL_CON2 0x010
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#define ARMPLL_LL_CON3 0x014
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#define ARMPLL_BL_CON0 0x008
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#define ARMPLL_BL_CON1 0x00c
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#define ARMPLL_BL_CON2 0x010
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#define ARMPLL_BL_CON3 0x014
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#define ARMPLL_B_CON0 0x008
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#define ARMPLL_B_CON1 0x00c
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#define ARMPLL_B_CON2 0x010
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#define ARMPLL_B_CON3 0x014
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#define CCIPLL_CON0 0x008
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#define CCIPLL_CON1 0x00c
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#define CCIPLL_CON2 0x010
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#define CCIPLL_CON3 0x014
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#define PTPPLL_CON0 0x008
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#define PTPPLL_CON1 0x00c
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#define PTPPLL_CON2 0x010
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#define PTPPLL_CON3 0x014
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#define MT8196_PLL_FMAX (3800UL * MHZ)
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#define MT8196_PLL_FMIN (1500UL * MHZ)
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#define MT8196_INTEGER_BITS 8
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#define PLL(_id, _name, _reg, _en_reg, _en_mask, _pll_en_bit, \
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_flags, _rst_bar_mask, \
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_pd_reg, _pd_shift, _tuner_reg, \
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_tuner_en_reg, _tuner_en_bit, \
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_pcw_reg, _pcw_shift, _pcwbits) { \
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.id = _id, \
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.name = _name, \
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.reg = _reg, \
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.en_reg = _en_reg, \
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.en_mask = _en_mask, \
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.pll_en_bit = _pll_en_bit, \
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.flags = _flags, \
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.rst_bar_mask = _rst_bar_mask, \
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.fmax = MT8196_PLL_FMAX, \
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.fmin = MT8196_PLL_FMIN, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.tuner_reg = _tuner_reg, \
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.tuner_en_reg = _tuner_en_reg, \
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.tuner_en_bit = _tuner_en_bit, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, \
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.pcwbits = _pcwbits, \
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.pcwibits = MT8196_INTEGER_BITS, \
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}
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static const struct mtk_pll_data cpu_bl_plls[] = {
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PLL(CLK_CPBL_ARMPLL_BL, "armpll-bl", ARMPLL_BL_CON0, ARMPLL_BL_CON0, 0,
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0, PLL_AO, BIT(0), ARMPLL_BL_CON1, 24, 0, 0, 0, ARMPLL_BL_CON1, 0, 22),
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};
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static const struct mtk_pll_data cpu_b_plls[] = {
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PLL(CLK_CPB_ARMPLL_B, "armpll-b", ARMPLL_B_CON0, ARMPLL_B_CON0, 0, 0,
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PLL_AO, BIT(0), ARMPLL_B_CON1, 24, 0, 0, 0, ARMPLL_B_CON1, 0, 22),
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};
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static const struct mtk_pll_data cpu_ll_plls[] = {
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PLL(CLK_CPLL_ARMPLL_LL, "armpll-ll", ARMPLL_LL_CON0, ARMPLL_LL_CON0, 0,
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0, PLL_AO, BIT(0), ARMPLL_LL_CON1, 24, 0, 0, 0, ARMPLL_LL_CON1, 0, 22),
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};
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static const struct mtk_pll_data cci_plls[] = {
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PLL(CLK_CCIPLL, "ccipll", CCIPLL_CON0, CCIPLL_CON0, 0, 0, PLL_AO,
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BIT(0), CCIPLL_CON1, 24, 0, 0, 0, CCIPLL_CON1, 0, 22),
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};
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static const struct mtk_pll_data ptp_plls[] = {
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PLL(CLK_PTPPLL, "ptppll", PTPPLL_CON0, PTPPLL_CON0, 0, 0, PLL_AO,
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BIT(0), PTPPLL_CON1, 24, 0, 0, 0, PTPPLL_CON1, 0, 22),
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};
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static const struct of_device_id of_match_clk_mt8196_mcu[] = {
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{ .compatible = "mediatek,mt8196-armpll-bl-pll-ctrl",
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.data = &cpu_bl_plls },
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{ .compatible = "mediatek,mt8196-armpll-b-pll-ctrl",
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.data = &cpu_b_plls },
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{ .compatible = "mediatek,mt8196-armpll-ll-pll-ctrl",
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.data = &cpu_ll_plls },
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{ .compatible = "mediatek,mt8196-ccipll-pll-ctrl", .data = &cci_plls },
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{ .compatible = "mediatek,mt8196-ptppll-pll-ctrl", .data = &ptp_plls },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_mcu);
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static int clk_mt8196_mcu_probe(struct platform_device *pdev)
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{
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const struct mtk_pll_data *plls;
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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const int num_plls = 1;
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int r;
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plls = of_device_get_match_data(&pdev->dev);
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if (!plls)
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return -EINVAL;
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clk_data = mtk_alloc_clk_data(num_plls);
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if (!clk_data)
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return -ENOMEM;
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r = mtk_clk_register_plls(node, plls, num_plls, clk_data);
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if (r)
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goto free_clk_data;
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r)
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goto unregister_plls;
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platform_set_drvdata(pdev, clk_data);
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return r;
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unregister_plls:
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mtk_clk_unregister_plls(plls, num_plls, clk_data);
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free_clk_data:
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mtk_free_clk_data(clk_data);
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return r;
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}
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static void clk_mt8196_mcu_remove(struct platform_device *pdev)
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{
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const struct mtk_pll_data *plls = of_device_get_match_data(&pdev->dev);
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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struct device_node *node = pdev->dev.of_node;
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of_clk_del_provider(node);
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mtk_clk_unregister_plls(plls, 1, clk_data);
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mtk_free_clk_data(clk_data);
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}
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static struct platform_driver clk_mt8196_mcu_drv = {
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.probe = clk_mt8196_mcu_probe,
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.remove = clk_mt8196_mcu_remove,
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.driver = {
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.name = "clk-mt8196-mcu",
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.of_match_table = of_match_clk_mt8196_mcu,
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},
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};
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module_platform_driver(clk_mt8196_mcu_drv);
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MODULE_DESCRIPTION("MediaTek MT8196 mcusys clocks driver");
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MODULE_LICENSE("GPL");

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